Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-05-08
2004-04-20
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S189040
Reexamination Certificate
active
06724668
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device provided with a plurality of memory chips.
2. Description of the Background Art
Conventionally, a semiconductor integrated circuit device having a plurality of memory chips of different kinds provided in one package is known. In such a conventional semiconductor integrated circuit device, a wafer test is conducted for each memory chip with an individual test standard, and a defective memory cell found is repaired by replacing it with a spare memory cell. Thereafter, the test is conducted again, and a memory chip whose memory cells are all normal is selected, which is then subjected to dicing and packaging. Here, to repair the defective memory cell, a laser trimming device is used to blow a fuse to program an address signal for the defective memory cell. When the relevant address signal is input, a spare memory cell is selected for replacement of the defective memory cell.
A memory cell may also become defective after packaging, due to various reasons. Thus, the test is conducted again after packaging, and only the semiconductor integrated circuit devices having the plurality of memory chips of different kinds with all the memory cells being normal are shipped as products.
With the conventional semiconductor integrated circuit devices, however, those found defective after packaging could not be repaired. Assuming that one semiconductor integrated circuit device has three memory chips incorporated therein, each with the yield after packaging of a%, b% and c%, respectively, then the overall yield thereof will be degraded to a%×b%×c%.
In addition, the test after packaging is likely to take a long time, since the plurality of memory chips incorporated in each semiconductor integrated circuit device should be tested one by one in series.
SUMMARY OF THE INVENTION
Based on the foregoing, a main object of the present invention is to provide a semiconductor device that assures a high yield, requiring a less test time.
The semiconductor device according to the present invention includes a plurality of memory chips, a tester circuit, a nonvolatile memory, and a transfer control circuit. Each memory chip includes: a plurality of memory cells; a spare memory cell; a holding circuit for holding an address signal of defective one of the memory cells; a memory cell select circuit selecting the spare memory cell when the address signal received matches the address signal held in the holding circuit, and selecting the memory cell corresponding to the received address signal when the received address signal differs from the address signal held in the holding circuit; and a write/read circuit performing writing/reading of a data signal with respect to the selected memory cell. The tester circuit tests the plurality of memory chips in parallel with each other, and obtains the address signal of the defective one of the plurality of memory cells in the respective memory chips. The nonvolatile memory stores the address signal obtained by the tester circuit. The transfer control circuit reads the address signal out of the nonvolatile memory, and transfers the address signal to the holding circuit of the memory chip corresponding to the relevant address signal. Accordingly, the address signal of the defective memory cell in each memory chip is obtained by the tester circuit, and the obtained address signal is stored in the nonvolatile memory. The address signal read out of the nonvolatile memory is transferred to the holding circuit in the corresponding memory chip, and the defective memory cell is replaced with the spare memory cell. Thus, even if a memory cell becomes defective after packaging, the defective memory cell can be replaced with the spare memory cell. This improves the yield of the semiconductor device. In addition, the tester circuit tests the plurality of memory chips in parallel. Therefore, compared to the case of testing the memory chips in series, the test time can be reduced.
Preferably, the tester circuit includes a plurality of sub-tester circuits provided corresponding to the plurality of memory chips. Each sub-tester circuit is provided to the corresponding memory chip for testing thereof, and obtains the address signal of the defective one of the plurality of memory cells in the corresponding memory chip. The nonvolatile memory includes a plurality of sub-nonvolatile memories provided corresponding to the plurality of memory chips. Each sub-nonvolatile memory is provided to the corresponding memory chip, and stores the address signal obtained by the corresponding sub-tester circuit. The address signal read out of each sub-nonvolatile memory is transferred to the corresponding holding circuit. In this case, the sub-tester circuit and sub-nonvolatile memory are provided for each memory chip, so that testing and repairing of the plurality of memory chips can readily be performed in parallel.
Still preferably, the tester circuit includes a plurality of sub-tester circuits provided corresponding to the plurality of memory chips. Each sub-tester circuit is provided to the corresponding memory chip for testing thereof, and obtains the address signal of the defective one of the plurality of memory cells in the corresponding memory chip. The nonvolatile memory is provided in predetermined one of the plurality of memory chips, and stores the address signal obtained by each sub-tester circuit. The holding circuits of the plurality of memory chips are connected in series. The address signal read out of the nonvolatile memory is transferred via one of the holding circuits to another one of the holding circuits. In this case, the nonvolatile memory is provided in one of the plurality of memory chips, so that the chip area of the other memory chip(s) can be reduced.
Still preferably, the tester circuit and the nonvolatile memory are provided in predetermined one of the plurality of memory chips. The holding circuits of the plurality of memory chips are connected in series. The address signal read out of the nonvolatile memory is transferred via one of the holding circuits to another one of the holding circuits. In this case, the tester circuit and the nonvolatile memory are provided in one memory chip. Thus, the chip area of the other memory chip(s) can further be reduced.
Still preferably, the semiconductor device further includes a test chip that is provided separately from the plurality of memory chips. The tester circuit is provided in the test chip. The nonvolatile memory is provided in predetermined one of the plurality of memory chips. The holding circuits of the plurality of memory chips are connected in series. The address signal read out of the nonvolatile memory is transferred via one of the holding circuits to another one of the holding circuits. In this case, the tester circuit is provided in the test chip independent from the memory chips. Thus, defectiveness of the tester circuit is prevented from causing defectiveness of the memory chip(s).
Still preferably, the predetermined memory chip is a flash memory, and the nonvolatile memory is a flash memory. In this case, the memory cells of the predetermined memory chip and of the nonvolatile memory can be manufactured in the same process. This leads to simplification of the manufacturing process.
Still preferably, the semiconductor device further includes a test chip provided separately from the plurality of memory chips, and the tester circuit and the nonvolatile memory are provided in the test chip. The holding circuits of the plurality of memory chips are connected in parallel with respect to the nonvolatile memory. The address signal read out of the nonvolatile memory is transferred directly to the corresponding holding circuit. In this case, the tester circuit and the nonvolatile memory are provided in the test chip independent from the memory chips. Thus, the tester circuit and the nonvolatile memory can be manufactured with optimal process rules. This preven
Kobayashi Shin-ichi
Ohmura Ryuji
Sugiura Kazushi
Auduong Gene
McDermott & Will & Emery
Renesas Technology Corp.
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