Semiconductor device provided with a level conversion means for

Details Semiconductor device provided with a level conversion means for Semiconductor device provided with a level conversion means for

1996-06-13

1998-03-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518911, 365203, 36523006, 326106, G11C 700, G11C 800

Patent

active

057269386

ABSTRACT:
A semiconductor device provided with a level inversion means comprising a transfer gate N4 for transmitting the output of an NAND circuit 1 to an inverter circuit 2, and a PMOS transistor P4 for pulling up the input terminal of the inverter circuit 2 up to VPP potential in response to the output data of the NAND circuit 1 when the input terminal of the inverter circuit 2 connected to the output terminal of the transfer gate is to be pulled up to the supply potential of VPP.

REFERENCES:
patent: 5490119 (1996-02-01), Sakurai et al.
patent: 5557580 (1996-09-01), Numaga et al.
"A High-Speed Ultra-Low Power 64k CMOS EPROM with On-Chip Test Functions" KNECT et al IEEE Journal of Solied-State Circuites, vol. Sci-18, No. 5 Oct. 1983, pp. 554-561.

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