Semiconductor device provided with a field-effect transistor...

Details Semiconductor device provided with a field-effect transistor... Semiconductor device provided with a field-effect transistor...

1999-10-06

2001-05-15

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S371000, C257S382000, C257S384000, C257S408000

Reexamination Certificate

active

06232640

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly a semiconductor device which can suppress generation of a leak current as well as a method of manufacturing the same.
2. Description of the Background Art
Semiconductor devices provided with field-effect transistors have been known.
FIG. 30
is a schematic cross section showing a semiconductor device in the prior art. Referring to
FIG. 30
, description will now be given on a conventional semiconductor device.
In
FIG. 30
, a semiconductor device is provided with field-effect transistors
138
a
and
138
b
formed on a semiconductor substrate
101
. Further, a p-well
102
and an n-well
103
are formed at semiconductor substrate
101
. An isolating oxide film
104
is formed at a main surface of semiconductor substrate
101
for isolating element formation regions from each other. In a region provided with p-well
102
, n
−
-type impurity diffusion regions
110
a
and
110
b
as well as n
+
-type impurity diffusion regions
111
a
and
111
b
are formed at the main surface of semiconductor substrate
101
. These n
−
-type impurity diffusion regions
110
a
and
110
b
as well as n
+
-type impurity diffusion regions
111
a
and
111
b
form source/drain regions. In a channel region located between n
−
-type impurity diffusion regions
110
a
and
110
b
, a gate electrode
106
a
is formed on the main surface of semiconductor substrate
101
with a gate insulating film
105
a
therebetween. Side walls
107
a
and
107
b
made of TEOS oxide films are formed on side surfaces of gate electrode
106
a
, respectively. High-melting-point metal silicide layers
108
a
-
108
c
are formed on gate electrode
106
a
and n
+
-type impurity diffusion regions
111
a
and
111
b
. Gate electrode
106
a
and gate insulating film
105
a
as well as source/drain regions
110
a
,
110
b
,
111
a
and
111
b
form field-effect transistor
138
a.
In the region provided with n-well
103
, p
−
-type impurity diffusion regions
112
a
and
112
b
as well as p
+
-type impurity diffusion regions
113
a
and
113
b
are formed at the main surface of semiconductor substrate
101
. These p
−
-type impurity diffusion regions
112
a
and
112
b
as well as p
+
-type impurity diffusion regions
113
a
and
113
b
form the source/drain regions. On a channel region located between p
−
-type impurity diffusion regions
112
a
and
112
b
, a gate electrode
106
b
is formed on the main surface of semiconductor substrate
101
with a gate insulating film
105
b
therebetween. Side walls
107
c
and
107
d
made of TEOS oxide films are formed on the side surfaces of gate electrode
106
b
, respectively. High-melting-point metal silicide layers
108
d
and
108
e
are formed on the p
+
-type impurity diffusion regions
113
a
and
113
b
, respectively. Gate electrode
106
b
, gate insulating film
105
b
and source/drain regions
112
a
,
112
b
,
113
a
and
113
b
form field-effect transistor
138
b
. A silicide protection film
109
made of a TEOS oxide film is formed on gate electrode
106
b
and source/drain regions
112
a
,
112
b
,
113
a
and
113
b.
An interlayer nitride film
114
, which serves as an etching stopper when forming an opening
129
, is formed on field-effect transistors
138
a
and
138
b
and isolating oxide film
104
. An interlayer insulating film
115
is formed on interlayer nitride film
114
. In a region located above n
+
-type impurity diffusion region
111
a
, interlayer insulating film
115
and interlayer nitride film
114
are partially removed by etching, and thereby an opening
129
is formed. A metal electrode
116
is formed in opening
129
and on interlayer insulating film
115
. An interconnection
130
is formed on interlayer insulating film
115
.
Referring to
FIGS. 31-35
, description will be given on steps of manufacturing the semiconductor device shown in FIG.
30
.
FIGS. 31
to
35
are schematic cross sections showing a method of manufacturing the semiconductor device shown in FIG.
30
.
First, isolating oxide film
104
(see
FIG. 31
) is formed at the main surface of semiconductor substrate
101
(see
FIG. 31
) to isolate the element formation regions from each other. Then, an ion implantation method is executed to form p- and n-wells
102
and
103
at the main surface of semiconductor substrate
101
. By thermally oxidizing the main surface of semiconductor substrate
101
, an oxide film which will form the gate insulating film is formed on the main surface of semiconductor substrate
101
. This oxide film has a film thickness of about several nanometers. A polycrystalline silicon film which will form the gate electrode is formed on this oxide film. This polycrystalline silicon film has a film thickness of about tens of nanometers. A resist pattern is formed on this polycrystalline silicon film. Using this resist pattern as a mask, etching is effected to remove portions of the polycrystalline silicon film and the insulating film so that gate insulating films
105
a
and
105
b
as well as gate electrodes
106
a
and
106
b
(see
FIG. 31
) are formed. Thereafter, the resist pattern is removed. An ion implanting method is executed to form n
−
-type impurity diffusion regions
110
a
and
110
b
as well as p
−
-type impurity diffusion regions
112
a
and
112
b
at the main surface of semiconductor substrate
101
. Thereafter, a TEOS oxide film
117
is deposited on gate electrodes
106
a
and
106
b
, the main surface of semiconductor substrate
101
and isolating oxide film
104
. TEOS oxide film
117
has a film thickness of about 60 nm. In this manner, the structure shown in
FIG. 31
is obtained.
As shown in
FIG. 32
, etchback is effected to remove partially TEOS oxide film
117
. Thereby, side walls
107
a
-
107
d
are formed on the side surfaces of gate electrodes
106
a
and
106
b
, respectively. The etching for removing TEOS oxide film
117
causes over-etching of about 40%. Therefore, the upper surface portion of isolating oxide film
104
is removed by a thickness A. More specifically, TEOS oxide film
117
is removed by about 60 nm in thickness, and a portion of thickness A (which is also referred to as a “removal thickness A” or a “drop amount” hereinafter) of about 25 nm is removed from isolating oxide film
104
.
As shown in
FIG. 32
, the ion implanting method is executed to implant n- and p-type impurities into the main surface of semiconductor substrate
101
. Thereby, n
+
-type impurity diffusion regions
111
a
and
111
b
as well as p
+
-type impurity diffusion regions
113
a
and
113
b
are formed.
As shown in
FIG. 33
, a TEOS oxide film
118
is then deposited on gate electrodes
106
a
and
106
b
, the main surface of semiconductor substrate
101
and isolating oxide film
104
. TEOS oxide film
118
has a film thickness of about 100 nm. A resist pattern
119
is formed on TEOS oxide film
118
.
Then, as shown in
FIG. 34
, TEOS oxide film
118
masked with resist pattern
119
is partially removed by etching so that silicide protection film
109
made of the TEOS oxide film is formed. Thereafter, resist pattern
119
is removed.
This etching for partially removing TEOS oxide film
118
likewise causes over-etching of about 40%. This over-etching removes the upper surface portion having a film thickness B from isolating oxide film
104
as shown in FIG.
34
. In this case, since TEOS oxide film
118
has a film thickness of 100 nm, and the removed portion of isolating oxide film
104
has film thickness B (which will also be referred to as a “removal thickness” or a “drop amount” hereinafter) of about 40 nm.
A high-melting-point metal film is formed on gate electrode
106
a
, the main surface of semiconductor substrate
101
, isolating oxide film
104
and silicide protection film
109
by a sputtering method. Lamp annealing is executed as thermal treatment. As a result, a si

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