Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-30
2003-05-06
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06559509
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device protection circuit. More particularly, the present invention relates to a semiconductor device protection containing a parasitic bipolar transistor.
2. Description of the Related Art
A protection circuit is widely used to avoid a semiconductor device from being damaged because of noise or static electricity.
FIG. 1
is a plan view illustrating a conventional protection circuit, which contains a parasitic NPN bipolar transistor.
FIGS. 2A and 2B
are sectional views showing the structure of the protection circuit.
FIG. 2A
shows the structure of a section along a D-D′ line in
FIG. 1
, and
FIG. 2B
shows the structure of a section along an E-E′ line in FIG.
1
.
A P-well
102
is formed in the surface portion of an N-type semiconductor substrate
101
. Active areas
600
,
700
and
800
are formed in the P-well
102
. The active areas
600
,
700
and
800
are separated by a field oxide film
103
formed in the surface portion of the P-well
102
. A channel stop
104
is formed immediately beneath the field oxide film
103
. The channel stop
104
is a heavily-doped P-type semiconductor.
As shown in
FIG. 2A
, a P+ region
105
is formed in the active area
600
. The P+ region
105
is a heavily-doped P-type semiconductor. The P+ region
105
is connected to the channel stop
104
.
An N+ region
106
is formed in the active area
700
. The N+ region
106
is a heavily-doped N-type semiconductor. The N+ region
106
is connected to the channel stop
104
.
The field oxide film
103
, the P+region
105
and the N+ region
106
are covered by an insulation film
108
. Contacts
109
,
110
are formed through the insulation film
108
. The P+ region
105
and the N+ region
106
are short-circuited to each other by a metallic wiring
111
through the contacts
109
,
110
.
On the other hand, an N+ region
107
is formed in the active area
800
, as shown in FIG.
2
B. The N+ region
107
is connected to the channel stop
104
. The N+ region
107
is covered by the insulation film
108
. Moreover, a contact
112
is formed through the insulation film
108
. The N+ region
107
is connected through the contact
112
to a metallic wiring
113
. The metallic wiring
113
is connected to an external connection terminal
114
and a semiconductor device (not shown), as shown in FIG.
1
.
The channel stop
104
, the P+ region
105
, the N+ region
106
and the N+ region
107
constitute a parasitic transistor, as shown in
FIGS. 2A and 2B
. The channel stop
104
functions as a P-type base of the parasitic transistor. The P+ region
105
functions as a heavily-doped P-type semiconductor for giving a potential to the base. The N+ region
106
functions as an emitter of the parasitic transistor. And, the N+ region
107
functions as a collector of the parasitic transistor.
The operations of the conventional protection circuit will be described below.
The metallic wiring
111
is grounded, and the P+ region
105
and the N+ region
106
are fixed to a ground potential. Moreover, a predetermined potential is given to the N-type semiconductor substrate
101
.
If an excessive voltage is applied to the external connection terminal
114
, the potential of the N+ region
107
is largely increased. At this time, as shown in
FIG. 2A
, a reverse bias is applied to a PN junction
115
composed of the channel stop
104
and the N+ region
107
. That is, the reverse bias is applied to a base-collector junction of the parasitic bipolar transistor. When the reverse bias becomes equal to or higher than a breakdown voltage, the PN junction
115
is broken down. If the PN junction
115
is broken down, a reverse bias current flows through the PN junction
115
. The reverse bias current flows through the channel stop
104
and the N+ region
106
into the metallic wiring
111
.
At this time, a potential drop resulting from a resistive component of the channel stop
104
causes a forward bias to be applied to a PN junction
116
composed of the N+ region
106
and the channel stop
104
. That is, the forward bias is applied to the base-emitter junction of the parasitic bipolar transistor.
As a result, the parasitic bipolar transistor amplifies the reverse bias current. Charges accumulated in the metallic wiring
113
quickly flow into the metallic wiring
111
. Thus, the potential of the metallic wiring
113
is quickly dropped to thereby protect the semiconductor device connected to the metallic wiring
113
.
Japanese Laid Open Patent Applications (JP-A-Heisei, 6-21076, 8-195442, and 10-163433) disclose other protection circuits for carrying out the similar operation.
It is desirable that the operation of such a protection circuit is stable. If light is incident on the P-well
102
and the channel stop
104
, electrons are generated in the P-well
102
and the channel stop
104
. The generation of the electrons causes the potential of the channel stop
104
to be easily varied. This results in an easy variation of a voltage at which the PN junction
115
composed of the channel stop
104
and the N+ region
107
is broken down. In the worst case, there may be a possibility that the operation of the conventional protection circuit is unstable to thereby bring about an optical latch-up. Hence, it is desirable that the operation of the protection circuit is stable even if the light is incident on the P-well
102
and the channel stop
104
.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to surely fix to a ground level a potential of a base of a protection circuit containing a parasitic bipolar transistor.
Another object of the present invention is to enable a stable operation of a protection circuit of a semiconductor device containing a parasitic bipolar transistor.
Still another object of the present invention is to protect an optical latch-up of a protection circuit of a semiconductor device containing a parasitic bipolar transistor.
In order to achieve an aspect of the present invention, a semiconductor device protection circuit is composed of a first semiconductor portion of a first conductive type, a second semiconductor portion of a second conductive type which is connected to the first semiconductor portion, a third semiconductor portion of the first conductive type which is connected to the second semiconductor portion, and fourth and fifth semiconductor portions of the second conductive type, both connected to the second semiconductor portion. The first conductive portion is connected to a semiconductor device which is to be protected from electrostatic breakdown. The third, fourth, and fifth semiconductor portions are short-circuited. The fourth and fifth semiconductor portions are located at opposite sides of the third semiconductor portion.
In the semiconductor device protection circuit of the present invention, the fourth and fifth semiconductor portions are located on both sides of the third semiconductor portion, which results in the stable potential of the second conductive portion. Thus, this stabilizes the operation of the semiconductor device protection circuit according to the present invention.
The third and fourth semiconductor portions may be substantially in contact with each other. In addition, the third and fifth semiconductor portions may be substantially in contact with each other.
When the third and fourth semiconductor portions are in contact with each other, a distance between the third and fourth semiconductor portions is the shortest, which results in the stable operation of the semiconductor device protection circuit of the present invention. Also, When the third and fifth semiconductor portions are in contact with each other, a distance between the third and fifth semiconductor portions is the shortest, which results in the stable operation of the semiconductor device protection circuit of the pr
Hatano Keisuke
Nakashiba Yasutaka
Fourson George
Garcia Joannie Adelle
NEC Corporation
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