Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-02-28
2003-05-27
Abraham, Fetsum (Department: 2826)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C257S296000, C257S297000, C257S298000, C257S299000, C257S300000, C257S072000
Reexamination Certificate
active
06569717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of producing a semiconductor device, to a method of producing an electro-optical device such as an active matrix driving liquid crystal device, to a semiconductor device, and to an electro-optical device. More particularly, the present invention relates to a semiconductor device and an electro-optical device, each having a thin film transistor (hereinafter also referred to as a TFT) and an additional storage capacitor both formed on a substrate, and also relates to a method of producing such a semiconductor device and a method of producing such an electro-optical device.
2. Description of Related Art
In a TFT-driven active matrix liquid crystal device according to a conventional technique, TFTs are disposed at respective intersections of a great number of scanning lines and data lines extending horizontally and vertically, respectively, wherein the gate electrode of each TFT is connected to one scanning line, the source region of each TFT is connected to one data line, and the drain region of each TFT is connected to one pixel electrode via a contact hole formed through an interlayer insulating film for electrically isolating various layers forming TFTs and interconnection lines and pixel electrodes. Thus, the pixel electrodes and the corresponding semiconductor layers are connected to each other through contact holes extending across a large interlayer distance of 1000 nm or greater. In particular, in the case of polysilicon TFTs of the normal stagger or coplanar type having a top gate structure in which the gate electrode is disposed above the semiconductor layer when seen from the side of the TFT array substrate, the interlayer distance of the contact holes becomes very long, and thus, it becomes difficult to form the contact holes. More specifically, because the etching accuracy becomes worse as the etching depth increases, there is a possibility that overetching occurs to a great extent, which causes a hole to be formed through the semiconductor layer. Thus, it is very difficult to form such a deep contact hole using only a dry etching process. One technique to solve the above problem is to employ a combination of dry etching and wet etching. However, this technique results in another problem in that the wet etching can cause the contact hole to be expanded in a lateral direction. As a result, it becomes difficult to form contact holes with a sufficiently small diameter, and thus, it becomes difficult to lay a required number of interconnections and electrodes in a limited area on a substrate.
The technique of connecting an additional storage capacitor to a TFT is employed not only in electro-optical devices, but also in semiconductor devices such as a dynamic type shift register or a DRAM (dynamic random access memory).
SUMMARY OF THE INVENTION
In general, in the art of electro-optical devices of the above-described type, there is a significant need for improvement in image quality. To this end, it is very important to achieve an image display area with a higher resolution by reducing the pixel pitch. It is also very important to increase the pixel aperture ratio (the ratio of an aperture area of a pixel through which image light can pass to a non-aperture area of the pixel through which image light cannot pass).
If the pixel pitch is reduced, interconnections and electrodes occupy a greater area in the image display area relative to the total image display area, because there are essential lower limits in the electrode size, the interconnection width and the contact hole diameter due to limitations of production technology. As a result, the pixel aperture ratio becomes low. Another problem resulting from the reduction in the pixel pitch is that it becomes difficult for a storage capacitor to have a sufficiently large capacitance to maintain a signal voltage applied to a pixel electrode, because the storage capacitor has to be formed in a smaller limited area on a substrate.
Also in other semiconductor devices such as a dynamic shift register or a DRAM having a storage capacitor, as in the pixel switching TFT described above, there is difficulty in reducing the feature size of circuit elements including storage capacitors due to a limitation of a processing technique of forming a contact hole reaching a semiconductor layer on a substrate.
In view of the above, it is an object of the present invention to provide a method of producing a semiconductor device and an electro-optical device capable of forming a good electrical connection between a pixel electrode or an interconnection line and a TFT, and also capable of forming a storage capacitor with an increased capacitance, thereby realizing a semiconductor device and an electro-optical device having high reliability by using a relatively simple structure having a small feature size of pixel pitch or circuit pitch.
According to an aspect of the present invention, to achieve the above object, there is provided a method of producing a semiconductor device, which may consist the steps of: forming a semiconductor layer on a substrate, the semiconductor layer serving as source and drain regions of a thin film transistor and a first capacitor electrode of a storage capacitor; forming a first insulating thin film on the semiconductor layer; forming a gate electrode and a second capacitance electrode of the storage capacitor, on the first insulating thin film, using the same film; forming a second insulating thin film on the surface of the gate electrode and on the surface of the second capacitor electrode; and forming a conductive layer serving as a third capacitor electrode of the storage capacitor, the conductive layer being connected to the semiconductor layer and opposing the second capacitor electrode via the second insulating thin film.
In this method, the first capacitor electrode is formed of the semiconductor layer which is also used to form the source and drain regions, the scanning line and the second capacitor electrode are formed of the same film, and the conductive layer serving as the third capacitor electrode is formed on the second capacitor electrode via the second insulating thin film such that a first storage capacitor is formed by the first and second capacitor electrodes and the first insulating thin film disposed between the first and second capacitor electrodes, and such that a second storage capacitor is formed by the second capacitor electrode and the conductive layer and the second insulating thin film disposed between the second capacitor electrode and the conductive layer. Thus, the storage capacitors can be easily formed using a process including a relatively small number of steps.
In particular, because the conductive layer is formed using a space on the second capacitor electrode instead of forming it on the gate electrode, it is possible to eliminate a parasitic capacitance which may occur between the gate electrode and the drain region connected to the conductive layer if the conductive layer is formed on the gate electrode. This makes it possible to prevent degradation in the image quality due to parasitic capacitance.
In a method of producing a semiconductor device according to another aspect of the present invention, the second insulating thin film includes an oxide film formed by oxidizing the surface of the gate electrode and the surface of the second capacitor electrode.
In this aspect, because the second insulating thin film serving as a dielectric film is formed by oxidizing the surface of the gate electrode and the surface of the second capacitor electrode, a high-quality interface having good uniformity and good adherence is obtained between the second insulating thin film realized in the form of an oxide film and the gate electrode and between the second insulating thin film and the second capacitor electrode. This resultant second insulating thin film has a low density of defects and has a high breakdown voltage, even if the thickness thereof is rather small. Thus, by partially using the condu
Abraham Fetsum
Oliff & Berridge PLC.
Seiko Epson Corporation
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