Semiconductor device preventing signal delay among wirings

Details Semiconductor device preventing signal delay among wirings Semiconductor device preventing signal delay among wirings

2001-12-13

2003-11-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S063000, C365S230060, C365S230080, C327S108000, C327S261000, C327S403000

Reexamination Certificate

active

06650574

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-314165, filed Oct. 11, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device adapted to, for example, a semiconductor memory, a logic circuit, an analogue circuit and the like.
2. Description of the Related Art
The processing technology for semiconductor devices has rapidly advanced in such a manner that it is now possible to form several hundreds of thousands of semiconductor devices within an area of 1 mm×1 mm. On the other hand, since the function of electronic equipment by which the semiconductor device is mounted has highly advanced, it is required for the semiconductor device of one chip has many functions. Thus, accompanying the increased number of functions is the related problem of chip size, which needs to be increased as a result. What is desired, however, is a size reduction.
Also, accompanying the increased chip size is the increased length of wiring inside the semiconductor device. Further, due to this fine processing, the current driving capacity of semiconductor devices has been improved and loads, such as gate capacitance, have been reduced. As a result, there are many cases where the operating speed of the semiconductor device depends on the signal delay in the wiring, rather than on the gate capacitance. Accordingly, in order to allow a semiconductor device to operate at high speed, it is required to reduce the signal delay in the wiring.
This signal delay is considered to have two causes. The first is the parasitic capacitance present in each wire and the second is the parasitic capacitance resulting from a plurality of activated wirings.
In order to control delays due to the first cause, a technology such as re-drive of the wiring, in which an amplifier is inserted in the middle of the wiring, can be used. For this reason, the solution is relatively simple. That is, the delay time of the wiring can be estimated from the product of resistance and capacitance of the wiring. For example, when a wiring resistance is taken as R and wiring capacity as C, the delay time &tgr; of the wiring is expressed by the following formula:
&tgr;=kRC
wherein k is a reasonable constant.
On the other hand, when the amplifier is inserted in the middle of the wiring, the delay time &tgr;
2
of the wiring is expressed by the following formula:
&tgr;
2
=k
(
R/
2·
C/
2)+
k
(
R/
2·
C/
2)
&tgr;
2
=&tgr;/2
In this way, by inserting the amplifier in the middle of the wiring and re-driving the wiring, it is possible to reduce the delay time of the signal propagated in the wiring by half the delay time of the case of the wiring only.
On the other hand, the delay time due to the second cause changes depending on the time relationship of the signals propagated respectively in a plurality of activated wirings. For this reason, it is difficult to control the delay time due to the second cause. This will be described below.
FIG. 13
shows two ordinary wirings adjacent to each other. Each wiring
11
,
12
has a resistance R and a parasitic capacity C, and a parasitic capacity Cc is coupled between the wiring
11
and the wiring
12
. These parasitic capacities are distributed capacities, and
FIG. 13
shows these distributed capacities by reference characters C, Cc for the sake of explanation. Drivers
13
,
14
having a current drive capacity of Idrv are inserted into each wiring
11
,
12
. These drivers
13
,
14
are constituted by an inverter circuit, for example, having two stages.
In the circuit constituted as described above, the delay time &tgr;
same
in driving each wiring
11
,
12
by the drivers
13
,
14
in the same direction and the delay time &tgr;
opposite
in driving in a different direction were simulated by using a circuit simulator.
FIG. 14
shows a simulation result of the circuit shown in FIG.
13
. In
FIG. 14
, the abscissa shows a transition time of the signal propagating in the adjacent wiring with a time difference “0” as a center. The ordinate shows the delay time of the signal propagating there. A minimum value of the delay time &tgr;
same
is approximately 250 p second, and the maximum value of the delay time &tgr;
opposite
is approximately 700 p second, and the difference between both of them amounts to approximately 450 p second. That is, corresponding to the operation of the signal propagating in the adjacent wiring, the delay time of the signal fluctuates within a range of two or more times the minimum value.
As described above, regarding the delay attributable to the parasitic capacity among a plurality of wirings, it is difficult to reduce the delay time only by inserting the amplifier in the middle of the wiring and re-driving the wiring.
That is, as shown in
FIG. 15
, amplifiers
13
-
1
,
14
-
1
constituted by two inverter circuits are inserted in the middle of the wirings
11
,
12
. In this constitution, by using the circuit simulator, a simulation was made similarly to the previous simulation.
FIG. 16
shows a simulation result of the circuit shown in FIG.
15
. The difference between the delay time &tgr;
same
and the delay time &tgr;
opposite
is approximately 350 p second and, compared to the result shown in
FIG. 14
, the fluctuation of the delay time is slightly reduced. However, the delay time in the worst condition in which the adjacent wiring operates in an antiphase in the entirely same timing is approximately 700 p second and does not differ from the result shown in FIG.
14
.
The re-drive technology of the wiring can narrow a range of the time difference of the signal due to the parasitic capacity among the wirings. However, it is not possible to control the magnitude of the delay time of the signal in the worst condition in which the signal of the adjacent wiring transits at approximately the same time and the magnitude of the fluctuation as a difference between the maximum value and the minimum value within the delay time in the same phase time and the delay time in the antiphase time (which includes a difference between the maximum value and the minimum value of the delay time in both the same phase time and the antiphase time, a difference between the maximum value and the minimum value of the delay time in the same phase time and a difference between the maximum value and the minimum value of the delay time in the antiphase time).
The most effective means as a method of controlling the influence of the coupling between the wirings is to provide a shield wire so as to reduce the coupling between the wirings. However, in this case, an extra wiring area is required for the purpose of shielding. In recent semiconductor devices, the main factor which decides the chip area is the wiring. In other words, the method of providing the shield wire creates the problem of increasing the tip area, thereby increasing the cost.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a semiconductor device comprising: a plurality of wirings which are arranged approximately in parallel and propagate a signal; and a first amplifier arranged in one wiring of two adjacent wirings which are included in a plurality of wirings, the first amplifier being arranged at least at a position which divides the interval of a predetermined distance of one wiring by 1
(n is an integer of two or more) and being constituted by an odd number of inverter circuits.


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