Semiconductor device package utilizing a solder flow prevention

Details Semiconductor device package utilizing a solder flow prevention Semiconductor device package utilizing a solder flow prevention

1990-07-27

1991-10-08

James, Andrew J.

357 80, H01L 2302, H01L 2312, H01L 3902

Patent

active

050559117

ABSTRACT:
A semiconductor package includes a base body, metallized layers formed on the base body and having a die-pad area and a wire bonding area, a solder flow prevention wall which is formed on the metallized layers between the die-pad area and a wire bonding area preventing solder from flowing to the wire bonding area while a semiconductor chip is being soldered to the die-pad area.

REFERENCES:
patent: 4067040 (1978-01-01), Tsuzuki et al.
patent: 4451845 (1984-05-01), Philofsky et al.
patent: 4672417 (1987-06-01), Sugiyama et al.
patent: 4692789 (1987-09-01), Nakamura et al.

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