Semiconductor device package

Details Semiconductor device package Semiconductor device package

2006-08-25

2009-06-02

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S723000, C257S685000, C257S686000, C257SE25006, C257SE25013, C257SE25027, C257SE23085

Reexamination Certificate

active

07541680

ABSTRACT:
Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

REFERENCES:
patent: 6979905 (2005-12-01), Nishida et al.
patent: 2001-257307 (2001-09-01), None
patent: 2004-235352 (2004-08-01), None
patent: 1020030048250 (2003-06-01), None

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