Semiconductor device outputting data at a timing with...

Details Semiconductor device outputting data at a timing with... Semiconductor device outputting data at a timing with...

2002-08-21

2004-05-25

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S230060

Reexamination Certificate

active

06741507

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to synchronous semiconductor devices synchronized with an external, periodically applied clock signal to take in an external signal. More specifically, it relates to synchronous dynamic random access memory (SDRAM) having a function to reduce fluctuation in access time introduced immediately after it returns from a power down mode.
2. Description of the Background Art
Dynamic random access memory (DRAM) used as main memory has been improved to operate faster. Its operating rate, however, still cannot catch up with that of a microprocessor (MPU). It is thus often said that the DRAM access time and cycle time are a bottleneck and thus impair a system's overall performance. In recent years as a main memory for a high speed MPU there has been proposed a double data rate (DDR) SDRAM operating in synchronization with a clock signal.
For the DDR SDRAM there has been proposed a specification allowing a rapid access for example to four successive bits in synchronization with both of two clock signals (extCLK, ext/CLK) to achieve rapid access.
FIG. 7
is a diagram for illustrating a waveform of an input/output in an normal operation of a conventional DDR SDRAM.
FIG. 7
shows that the DDR SDRAM, capable of inputting and outputting data of eight bits (bite data) of data input/output terminals DQ
0
-DQ
7
, reads/writes four data (of 8×4 equal to 32 bits in total) successively. The number of bits of data read successively is referred to as a burst length and for a DDR SDRAM, typically it is variable depending on the setting of a mode register.
With reference to
FIG. 7
, at time t
1
an external clock signal extCLK has a rising edge and external control signals (a row address strobe signal /RAS, a column address strobe signal /CAS, an address signal Add. and the like) are taken in. Since row address strobe signal /RAS has a low level of an active state, the current address signal Add. is taken in as a row address Xa. Note that address signal Add. includes address signals A
0
-A
10
and a bank address signal BA.
At time t
2
column address strobe signal /CAS attains a low level of an active state and in synchronization with clock signal extCLK going high column address strobe signal /CAS is internally taken in. The current address signal Add. is taken in as a column address Yb. In response to the row and column addresses Xa and Yb taken in, the DDR SDRAM internally effects a row and column select operation.
D/Q represents data signals DQ
0
-DQi input/output to/from an input/output terminal. After row address strobe signal /RAS falls to the low level when a predetermined clock cycle (3.5 clock cycles in
FIG. 7
) elapses or time t
4
arrives, initial data q
0
is output and followed by data q
1
-q
3
output successively.
The data are output in response to clock signals extCLK and ext/CLK crossing each other. To allow data to be transferred rapidly, a data strobe signal DQS is output in phase with output data.
Note that at time t
3
when clock signal extCLK has a rising edge, control signals /RAS and /WE are set low and a re-write to a memory cell (or a precharge) is effected.
At time t
5
and thereafter, a write operation is represented. At time t
5
a row address Xc is taken in. At time t
6
when column address strobe signal /CAS and write enable signal /WE are both set to have the low level of the active state, in response to the current clock signal extCLK having a rising edge a column address Yd is taken in. Then the currently provided data d
0
is taken in as initial write data. In response to row and column address strobe signal /RAS and /CAS falling, the DDR SDRAM internally effects a row and column select operation. Subsequently in synchronization with data strobe signal DQS input data d
1
-d
3
are successively taken in and written to a corresponding memory cell.
To achieve a high data transfer rate, data is read and written in synchronization with a clock signal having a high frequency. Implementing a steady system operation with a high frequency requires a DDR SDRAM to be internally timed as defined more strictly.
To reduce fluctuation in data access time in a read, a delay locked loop (DLL) circuit is typically used. The amount of delay of the DLL circuit, however, fluctuates with noise generated in a power supply potential. Accordingly, the DLL circuit receives as an operating power supply voltage an internal power supply voltage stabilized by a regulator.
FIG. 8
is a circuit diagram for illustrating a first example of a connection of the regulator and the DLL circuit.
With reference to
FIG. 8
, a regulator
500
receives an external power supply voltage EXTVDD and supplies a clock input buffer
509
, an inverter
507
and a DLL circuit
510
with an internal power supply potential INTVDD. Clock input buffer
509
externally receives complementary clock signals extCLK, ext/CLK and detects a point at which the clock signals cross each other. Inverter
507
receives an output from clock input buffer
509
, inverts it and outputs a clock signal ECLK. DLL circuit
510
responds to clock signal ECLK by outputting an internal clock signal INTCLK (not shown). Clock signal INTCLK provides a reference timing applied to externally output data from a data output buffer.
Clock input buffer
509
includes an n channel MOS transistor
506
having a source connected to a ground node and a gate receiving a clock enable signal extCKE, an n channel MOS transistor
503
having a source connected to a drain of n channel MOS transistor
506
and a gate receiving clock signal ext/CLK, and a p channel MOS transistor
501
having a gate and drain connected to a drain of n channel MOS transistor
503
and a source receiving an internal power supply potential from regulator
500
.
Clock input buffer
509
also includes an n channel MOS transistor
504
having a source connected to a drain of n channel MOS transistor
506
and a gate receiving clock signal extCLK, and a p channel MOS transistor
502
connected to a drain of n channel MOS transistor
503
and having a gate connected to a drain of n channel MOS transistor
503
and a source receiving an internal power supply potential from regulator
500
.
N channel MOS transistor
504
has a drain connected to an input of inverter
507
.
FIG. 9
is a circuit diagram showing a second example of the connection of the regulator and the DLL circuit.
With reference to
FIG. 9
, regulator
500
receives external power supply potential EXTVDD and provides internal power supply potential INTVDD to DLL circuit
510
. Clock input buffer
509
and inverter
507
directly receive external power supply potential EXTVDD as an operating power supply potential.
Clock input buffer
509
is configured and clock input buffer
509
, inverter
507
and DLL circuit
510
are connected, as shown in FIG.
8
.
FIG. 10
is a block diagram showing a configuration of DLL circuit
510
shown in
FIGS. 8 and 9
.
With reference to
FIG. 10
, DLL circuit
510
includes a delay line
530
delaying clock signal ECLK and outputting an internal clock signal INTCLK, a delay circuit
532
delaying internal clock signal INTCLK to output a clock signal RCLK, a phase comparator
522
comparing a phase of clock signal ECLK and that of clock signal RCLK and outputting control signals UP and DOWN, a digital filter
526
receiving an output from phase comparator
522
, filtering it and outputting control signals UP_D and DOWN_D, and a counter and decoder
528
driven by an output of digital filter
526
to change an internal count value to determine a delay time for delay line
530
.
FIG. 11
is a circuit diagram showing a configuration of digital filter
526
shown in FIG.
10
.
With reference to
FIG. 11
, digital filter
526
includes a shift register
52
providing an output set high when control signal UP is activated twice in pulses, an AND circuit
560
receiving an output from shift register
52
and control signal UP and outputting control signa

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