Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2006-08-15
2006-08-15
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257SE21238, C257SE21596, C257SE23179, C438S114000, C438S462000, C438S465000, C438S975000
Reexamination Certificate
active
07091624
ABSTRACT:
A semiconductor chip is formed by dividing a semiconductor wafer by use of the laser dicing technique. The semiconductor chip has a laser dicing region on the side surface thereof. A dummy wiring layer is formed along the laser dicing region on the surface layer of the laser dicing region. A laser beam is applied to the dummy wiring layer to divide the semiconductor wafer.
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Notification of Reasons for Rejection from the Japanese Patent Office dated Nov. 22, 2005, in patent application No. 2003-006387, and English translation thereof.
Iijima Toshitsune
Sato Ninao
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Fourson George
Garcia Joannie Adelle
Kabushiki Kaisha Toshiba
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