Semiconductor device, method of testing the same and...

Details Semiconductor device, method of testing the same and... Semiconductor device, method of testing the same and...

2006-08-01

2006-08-01

Chung, Phung My (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07085974

ABSTRACT:
A semiconductor device having a plurality of memory cells for storing data, an address input circuit having an address signal generation section for independently generating an address signal using a clock signal in a test mode, and a delay circuit for delaying an input time of the address signal from the address input circuit to a subsequent circuit for a predetermined time period which is equal to or longer than the time necessary for the generation of the address signal.

REFERENCES:
patent: 6473455 (2002-10-01), Kwon
patent: 6594186 (2003-07-01), Kodaira et al.
patent: 2003/0026149 (2003-02-01), Braceras et al.
patent: 04-061420 (1992-02-01), None
patent: 10-172298 (1998-06-01), None
patent: 11-185497 (1999-07-01), None
patent: 2001-236797 (2001-08-01), None
U.S. Appl. No. 10/171,421, filed Jun. 12, 2002, Kodaira, et al.

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