Semiconductor device, method of manufacturing the same, and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

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Details

C438S151000, C438S301000, C257S336000

Reexamination Certificate

active

07344931

ABSTRACT:
The present invention is directed to a method of manufacturing a semiconductor device including a semiconductor layer having a heavily doped source region, a heavily doped drain region, a lightly doped source region, a lightly doped drain region and a channel region, and a gate electrode opposite to the semiconductor layer with an insulating layer interposed therebetween. The method includes forming a semiconductor film on a substrate, forming a resist on the semiconductor film such that a first portion of the resist corresponding to the heavily doped source region and the heavily doped drain region is thinner than a second portion of the resist corresponding to the lightly doped source region, the lightly doped drain region and the channel region. In addition, the method includes forming the heavily doped source region and the heavily doped drain region by etching the semiconductor film in a predetermined pattern using the resist as a mask and injecting high density impurities into the semiconductor film through the first portion of the resist, removing the resist from the semiconductor film to form a gate insulating layer on the semiconductor film. Further, the method includes forming the gate electrode at a position on the gate insulating layer which corresponds to the channel region, and forming the lightly doped source region and the lightly doped drain region by injecting impurities having a density lower than the density of the high density impurities into the semiconductor film using the gate electrode as a mask.

REFERENCES:
patent: 6049092 (2000-04-01), Konuma et al.
patent: 6133074 (2000-10-01), Ishida et al.
patent: 6617644 (2003-09-01), Yamazaki et al.
patent: 6867431 (2005-03-01), Konuma et al.
patent: 7172928 (2007-02-01), Yamazaki
patent: 2002/0025591 (2002-02-01), Ohnuma et al.
patent: 2002/0134983 (2002-09-01), Yamazaki
patent: 2002-151523 (2002-05-01), None

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