Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – On insulating carrier other than a printed circuit board
Reexamination Certificate
2001-05-30
2004-06-01
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
On insulating carrier other than a printed circuit board
C257S676000, C257S688000, C257S694000, C257S737000, C257S738000, C257S739000, C257S774000
Reexamination Certificate
active
06744122
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of fabricating the semiconductor device, a circuit board, and an electronic instrument.
BACKGROUND ART
As one type of CSP (Chip Scale/Size Package) semiconductor devices, a semiconductor device with a structure in which a semiconductor chip is mounted face-down to a substrate has been known. In such a face down structure, a semiconductor chip is generally mounted on a surface of the substrate on which an interconnecting pattern is formed. Therefore, since part of the interconnecting pattern is covered with the semiconductor chip, the degree of freedom in designing the interconnecting pattern is limited.
DISCLOSURE OF THE INVENTION
The present invention has been achieved to solve this problem. An objective of the present invention is to provide a semiconductor device and a method of fabricating the same capable of increasing the degree of freedom in designing an interconnecting pattern without decreasing connection reliability, a circuit board, and an electronic instrument.
(1) According to the present invention, there is provided a semiconductor device comprising:
a substrate including a plurality of holes and a surface over which an interconnecting pattern is formed, part of the interconnecting pattern extending over the holes;
a semiconductor chip disposed over another surface of the substrate and including a plurality of electrodes to be positioned over the holes; and
conductive members provided within the holes for electrically connecting the electrodes to the interconnecting pattern.
According to the present invention, the conductive members formed on the electrodes of the semiconductor chip are disposed within the holes and connected to the interconnecting pattern. Therefore, the interconnecting pattern is located on the side of the substrate opposite to the mounting region of the semiconductor chip. Specifically, since the interconnecting pattern is not covered with the semiconductor chip, the interconnecting pattern can be designed without limitation. Moreover, there is a substrate between the interconnecting pattern and the semiconductor chip. Therefore, signals in an integrated circuit in the semiconductor chip scarcely interfere with signals in the interconnecting pattern, whereby cross talk can be reduced. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained without decreasing connection reliability.
(2) In this semiconductor device, a resin may be provided between the substrate and the semiconductor chip.
According to this semiconductor device, the semiconductor chip is mounted on a surface of the substrate on which the interconnecting pattern is not required, and a resin is provided between the substrate and the semiconductor chip. Therefore, if an interconnecting pattern is not formed over the surface of the substrate over which the semiconductor chip is mounted, the resin is provided on the substrate exhibiting comparatively excellent adhesion, so that delamination can be reduced. Because of this, a semiconductor device with an increased degree of freedom in designing the interconnecting pattern can be obtained more effectively without decreasing connection reliability.
(3) In this semiconductor device, the resin may be an anisotropic conductive material containing conductive particles; and the conductive members may be electrically connected to the interconnecting pattern through the conductive particles.
(4) In this semiconductor device, part of the interconnecting pattern may close the holes.
(5) In this semiconductor device, the interconnecting pattern may include a plurality of interconnecting lines; and
two or more interconnecting lines may extend over each of the holes.
This enables holes necessary for the substrate can be easily formed.
(6) In this semiconductor device, the other surface of the substrate may be roughed.
Since a contact area between the resin and the substrate is increased, adhesion between them can be further improved.
(7) In this semiconductor device, a recognition hole may be formed in the substrate at a position differing from the holes; and
a recognition pattern may be formed over the recognition hole on the side of a surface of the substrate including the interconnecting pattern.
This enables to mount the semiconductor chip easily over the substrate.
(8) In this semiconductor device, the recognition hole may be formed in the substrate outside a mounting region for the semiconductor chip.
This makes it possible to mount the semiconductor chip easily over the substrate.
(9) In this semiconductor device, the recognition pattern may includes:
a first pattern extending in the X-axis direction of the two-dimensional coordinate system established on a surface of the substrate; and
a second pattern extending in the Y-axis direction.
This enables the semiconductor chip to be accurately mounted at a given position on the substrate by recognizing the first and second patterns.
(10) In this semiconductor device, the conductive members may be a plurality of layered bumps.
This enables the conductive members to be formed by using existing techniques and devices, for example.
(11) In this semiconductor device, the bumps may include first bumps formed on the electrodes and second bumps formed on the first bumps.
Note that the first and second bumps refer to two arbitrary bumps, and this is applicable to two or more bumps.
(12) In this semiconductor device, at least the first bumps may be ball bumps.
According to this semiconductor device, the first bumps may be formed by the ball bump method. Since existing wire bonder devices can be utilized, the semiconductor device can be fabricated with reduced equipment investment.
(13) In this semiconductor device, the second bumps may be formed of a metal which has a melting point lower than the melting point of the first bumps.
According to this semiconductor device, since the first bumps formed in advance have a higher melting point, the first bumps are less affected by heat for forming the second bumps, for example. Therefore, a plurality of bumps can be easily layered.
(14) In this semiconductor device, the first bumps may be formed of gold.
Gold has a comparatively high melting point.
(15) In this semiconductor device, the second bumps may be formed of solder.
(16) In this semiconductor device, the first bumps and the second bumps may be formed of the same material.
This enables the second bump to also be formed by the ball bump method, for example.
(17) In this semiconductor device, the semiconductor chip may be mounted face-down to the substrate.
According to this semiconductor device, the interval between the semiconductor chip and the substrate is increased by the height of the first and second bumps formed on the electrodes of the semiconductor chip, so a large amount of resin can be provided right under the semiconductor chip, thereby enabling the resin to fully function as a stress relaxation layer. If the first bump is formed of gold and the second bump is formed of solder, a mounting structure of solder bumps with a core (gold) can be easily obtained.
(18) According to the present invention, there is provided a circuit board over which the above-described semiconductor device is mounted.
(19) An electronic instrument according to the present invention is provided with the above semiconductor device.
(20) According to the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
preparing a substrate including a plurality of holes and an interconnecting pattern which extends partially over the holes, and also preparing a semiconductor chip having a plurality of electrodes which have conductive members formed on the electrodes; and
disposing the conductive members within the holes and mounting the semiconductor chip over the substrate to connect electrically the interconnecting pattern to the electrodes through the conductive members.
According to the present invention, the conducti
Seiko Epson Corporation
Tran Minhloan
Tran Tan
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