Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2011-05-31
2011-05-31
Estrada, Michelle (Department: 2829)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S418000, C438S761000, C438S962000, C257SE29168, C257SE33008, C257SE31033, C257SE29069
Reexamination Certificate
active
07951684
ABSTRACT:
A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6′), wherein the material of the insulating layers (6,6′) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths.In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
REFERENCES:
patent: 5359617 (1994-10-01), Kano et al.
patent: 5565693 (1996-10-01), Sasaki et al.
patent: 7105895 (2006-09-01), Wang et al.
Estrada Michelle
NXP B.V.
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