Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-30
2007-01-30
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10634988
ABSTRACT:
To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high.A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.
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Ito Mitsumi
Mukai Kiyohito
Shimada Jun'ichi
Tsujikawa Hiroyuki
McDermott Will & Emery LLP
Whitmore Stacy A
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