Semiconductor device manufacturing method to reduce process...

Details Semiconductor device manufacturing method to reduce process... Semiconductor device manufacturing method to reduce process...

2000-05-03

2003-02-04

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S424000, C438S435000, C438S437000, C257S510000

Reexamination Certificate

active

06514885

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, and more particularly to a semiconductor device manufacturing method for improving reliability by reducing crystalline defects in scaled devices and process induced stress.
2. Description of the Prior Art
The semiconductor fabrication process has been composed basically of diffusion, silicidation, oxidation, chemical vapor deposition (CVD), ion implantation, etching and so-forth, done repeatedly on semiconductor silicon substrates.
At a scaled geometry of 0.25 &mgr;m or smaller, however, stress and crystalline defects in the silicon substrate and device itself begin to predominate. These stress and crystalline defects play a role in device operation reliability, such as mobility reduction in channel region of MOS devices due to scattering, leakage current in P/N junction, and so-forth. Thus, stress and crystalline defects are very important issue in both process and device designing. Complicating matters is the fact that stress and crystalline defects are ‘invisible’ and very difficult to detect in fabrication lines. Heretofore, process induced stress and crystalline defects have neither been controlled nor analyzed.
Among a series of LSI processes, RTP(rapid thermal process), RIE(reactive ion etching), shallow trench isolation process, and silicidation have been thought to be primary factors causing crystalline defect. In addition, appearance of crystalline defects has been thought in connection with mechanical strength of Si wafer itself. However, this is still qualitatively discussion.
For high packing density LSI, isolation process which makes devices electrically isolated from each other on a semiconductor chip is one of the key issues. Before a generation of 0.25 &mgr;m-devices, there had been adopted the LOCOS (locally oxidation process) isolation process. However, the LOCOS process requires a large area on the silicon substrate devoted to isolation. This is a serious disadvantage for high density scaled MOS/Bipolar devices, such as 0.25 &mgr;m. Consequently, a new candidate for isolation process has been developed. This is the STI (shallow trench isolation) process The STI process is the ultimate ideal process, because trenches are made between each individual device on silicon substrate, and filled with insulating material. However, for STI there is a problem of the difference in thermal expansion coefficient. Thermal coefficient of Si is of 3.052×10
−6
, and that of SiO
2
is of 1.206×10
−7
. Thus, it can be seen that a large number of stress has been generated due to the difference in thermal expansion coefficients.
Heretofore, some researchers have analyzed the stress distribution around STI in terms of process temperature and materials for filling to some extent. According to the prediction of process simulators, one can modify and optimize the process sequence and structure of STI in advance of actual fabrication. However, since process sequences to suppress dislocation generation are not completely controlled, there are still some important factors remaining.
Reference is made to K. Schonenberg, ‘Stability of Size Strained Layers on Small Areas Trench Isolated Silicon Islands’, Proceedings of the Fourth International Symposium on Process Physics and Modeling in Semiconductor Technology. Electrochemical Society vol.96-4, p.298. This paper describes efforts to overcome existing problems.
FIGS. 1
,
2
, and
3
herein are reproduced from the paper.
FIG. 1
shows a cross section TEM (Transmission Electron Microscope) photo of STI. It can be seen from the photo that most dislocations are observed to be around the comers of the STI. The authors of the paper have focused on the dislocation line on [110]Si direction. Moreover, they said that slip plane was on (111)Si. They speculated dislocation generated due to shear stress on (111)Si plane. In
FIG. 3
, they reported that dislocation loops were observed. However, the cause of the dislocations was not explained. Thus, it is still difficult to propose modification of process sequence and STI structure to eliminate defects.
Another prior art reference is I. V. Peidous, R. Sundaresan, E. Quek, Y. K. Leung, M. Beh, (Singapore). ‘Impact of Silicon Wafer Material on Dislocation Generation in Local Oxidation’. Silicon Front-end Technology-Materials Processing and Modeling,
Mat.Res. Soc. Symp. Proc.,
vol. 532, (1998) p.125. Two typical figures from the paper are reproduced in FIG.
4
and
FIG. 5
herein.
FIG. 4
shows an optical microscope photo on the top view of the Si chip.
FIG. 5
is an optical microscope photo, in which dislocation etch pits have been observed. In this paper, they estimated value of the stress which generate dislocations based on the etch pit spacing. The basic theory for the stress estimation based on etch pit spacing has been well recognized and it is discussed in ‘Theory of Dislocations’, Second Edition, J. P. Hirth, Krieger Publishing Company, 1992. ISBN-0-89464-617-6. However, they still have difficult to pick up new definite ideas which feedback to process sequence. Moreover, there is still problems remaining unsolved when dislocations are generated. Therefore, as seen from the above, current understanding for stress and dislocation generation has still been in only observation phase and phenomenological discussion phase.
Yet another prior art reference is a discussion of dislocation generation from a view point of device fabrication; G. Ho, E. Hammerl, R. Stengl, and J. Benedict(IBM, Siemens) ‘Dislocation Formation in Trench-Based Dynamic Random Access Memory (DRAM) Chips’. Surface/interface and Stress Effects in Electronic Material Nanostructures,
Mat.Res. Soc. Symp. Proc.
vol. 405, (1996). p.459. Some typical figures from the reference are shown in FIGS.
6
(
a
), (
b
), (
c
), and (
d
). The authors discussed dislocation generation probability in terms of cell arrays, such as half pitch layout, quarter pitch layout. According to their analysis and discussion, dislocation generation has been found to have strong correlation with cell patterns and layout. Through their discussion and analysis, some of the dislocations have been observed in optimized cell structure. From the sense of reliability of device such as 256MdRAM, 1GdRAM, and more, however, a much more reliant process must be established.
As noted in above, three dimensional process simulators have been now available to estimate distribution of stress generated during oxidation, diffusion and so-forth. In recent years, three dimensional process simulator is one of the tools to estimate structure and stress distribution. This tool is very useful for making process sequence in advance of actual fabrication. However, the output is still not satisfactory. The accuracy is currently around 50%. Therefore, at this moment, the full development of 0.25 &mgr;m device or smaller geometry is still retarded.
Four prior references on the silicidation process are discussed. First is J. A. Kittl, Q. Z. Hong, H. Yang, N. Yu, M. Rodder, P. P. Apte, W. T. Shiau, C. P. Chao, T. Breedijk and M. F. Pas (TI). ‘Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 □m CMOS’. Advanced Interconnects and Contact Materials and Processes for Future Integrated Circuit,
Mat.Res. Soc. Symp. Proc.
vol. 514, (1998) p.255. In this paper, they present studies of Ti and Co salicide processes implemented into a 0.10 &mgr;m CMOS technology. The paper focused on morphology and sheet resistively. The paper did not disclose silicidation induced stress distribution nor dislocation.
A second reference is; K. Suguro, T. Iinuma, K. Ohuchi, K. Miyashita, H. Akutsu, H. Yoshimura, Y. Akasaka, K. Nakajima, K. Miyano, and Y. Toyoshima. (Toshiba). ‘Silicide Technology in Deep Submicron Regime’. Advanced Interconnects and Contact Materials and Process for Future Integrated Circuits.
Mat.Res. Soc. Symp. Proc.
vol. 514, (1998) p.171. This paper said that silicide technology using cobalt-titanium alloy ha

Affiliated with

Also associated with

Rating

Semiconductor device manufacturing method to reduce process... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device manufacturing method to reduce process..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device manufacturing method to reduce process... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3166251