Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-08-21
2007-08-21
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S640000, C438S736000, C257SE21579
Reexamination Certificate
active
11032015
ABSTRACT:
A semiconductor device manufacturing method includes the steps of: forming first and second insulation films on a substrate provided with a first wiring; sequentially forming first to third mask layers on the second insulation film; forming a wiring groove pattern in the third mask layer; selectively processing the third mask layer, formed to project into the inside of the wiring groove pattern, into a tapered shape; forming a contact hole pattern in the second and first mask layer, and removing the tapered shape portions of the third mask layer; and forming wiring grooves in the second insulation film by etching using the third mask layer, and forming contact holes in the insulation film by etching using the second and first mask layers.
REFERENCES:
patent: 6514867 (2003-02-01), Hui et al.
patent: 6593246 (2003-07-01), Hasegawa et al.
patent: 6627557 (2003-09-01), Seta et al.
patent: 6743712 (2004-06-01), Park et al.
patent: 2001/0046783 (2001-11-01), Furusawa et al.
patent: 2006/0166482 (2006-07-01), Kanamura
patent: 11-045887 (1999-02-01), None
patent: 2000-150519 (2000-05-01), None
patent: 2001-044189 (2001-02-01), None
patent: 2001-077196 (2001-03-01), None
patent: 2001-156170 (2001-06-01), None
patent: 2002-124568 (2002-04-01), None
patent: 2003-297920 (2003-10-01), None
patent: 2003-303824 (2003-10-01), None
“Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SIOC Hybrid Structure for 65nm-node High Performance eDRAM”, R. Kanamura et al, 2003 Symposium on VSI Technology Digest of Technical Papers, pp. 107-108 (2003).
Japanese Office Action; Application No.: 2004-010362; dated Jan. 23, 2007.
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Smoot Stephen W.
Sony Corporation
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