Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-29
2002-08-20
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000
Reexamination Certificate
active
06436806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device in which electrical shorts between lower and upper interconnection layers, caused by the flow of an intermediate borophosphosilicate glass (BPSG) layer, can be reduced or prevented.
2. Description of the Related Art
In manufacturing a stacked semiconductor device, planarization of interlevel dielectric films (ILDs) must be performed to ensure a sufficient processing margin for subsequent photolithography and etch steps to provide increased reliability of the resulting semiconductor devices. As the integration density of semiconductor devices continues to increase, even greater interest has been focused on the planarization of ILDs.
A typical ILD planarization technique is to use a high-fluidity or reflowable layer such as a borophosphosilicate glass (BPSG) layer. In planarizing ILDs with a BPSG layer, deposition of the BPSG layer is followed by a thermal process for reflowing the BPSG layer.
FIG. 1
is a sectional view of a conventional semiconductor device with a BPSG layer as a planarization layer.
As shown in
FIG. 1
, isolation layers
2
are appropriately located in a semiconductor substrate
1
to define an active area. A gate electrode
4
on a gate oxide layer
3
is formed in the active area of the semiconductor substrate
1
by conventional processes using a hard mask oxide layer
5
as an etching mask. A pair of spacers
7
is then formed on the sidewalls of the hard mask oxide layer
5
and the gate electrode
4
. Source and drain regions
6
a
and
6
b
are formed at both sides of the gate electrode
4
in the active area, to produce the basic transistor structure.
A first insulating layer
8
is then deposited on the semiconductor substrate
1
such that the transistor is fully covered. A BPSG layer
9
provided as a planarization layer is deposited on the first insulating layer
8
and then flowed at a temperature of 820° C. or more, so that the surface of the BPSG layer
9
is planarized. A second insulating layer
10
is deposited on the planarized BPSG layer
9
. This second insulating layer
10
serves to prevent out diffusion of boron or phosphorous from the BPSG layer
9
.
An interconnection layer is formed on a portion of the second insulating layer
10
. The interconnection layer is then patterned and etched to form an interconnector structure
11
that is aligned above the gate electrode
4
. It is preferable that the interconnection layer is formed of polysilicon. The interconnection layer can also comprise other conductors such as tungsten silicide (WSi
x
), cobalt silicide (CoSi
x
), or titanium silicide (TiSi
x
). A third insulating layer
12
is deposited on the second insulating layer
10
such that the interconnection layer
11
is fully covered. The third and second insulating layers
12
and
10
, the BPSG layer
9
, and the first insulating layer
8
are then etched to form contact holes
13
through which the source and drain regions
6
a
and
6
b
are exposed. A metal layer is then deposited on the third insulating layer
12
, filling the contact holes
13
, and patterned and etched to form metal electrodes
14
, which contact the source and drain regions
6
a
and
6
b.
In the conventional semiconductor device described above, an electrical short between the interconnection layer
11
and the metal electrodes
14
may form as the result of undesirable flowing of the BPSG layer during subsequent thermal processes. In other words, if the initial post-deposition reflow of the BPSG layer
9
is not sufficient, a secondary flowing of the BPSG layer
9
can occur during thermal processes subsequent to the formation of the interconnection structure
11
. As a result, the interconnection structure
11
formed on the BPSG layer
9
can migrate or shift closer to one of the metal interconnection layers
14
, thereby causing an electrical short.
It is therefore preferable that the initial reflow of the BPSG layer
9
occurs at a high temperature of 820° C. or more to ensure that the flowing of the BPSG layer
9
is substantially complete and not likely to subject to secondary flowing during subsequent processes. Unfortunately, when temperatures of 820° C. or more are utilized to reflow the BPSG layer
9
, the high levels of impurities contained in the BPSG layer
9
, particularly boron and phosphorous, can diffuse into the gate electrode
4
. The presence of these dopants in the gate electrode will degrade the electrical characteristics of the resulting semiconductor device, for example, by rendering the transistor threshold voltage unstable or variable.
To prevent this degradation in the electrical characteristics of the resulting semiconductor devices, the BPSG layer
9
is typically reflowed at a temperature of 820° C. or less even though at this temperature the BPSG layer
9
will not fully flow. Accordingly, the incompletely reflowed BPSG layer
9
will tend to undergo additional flow during subsequent thermal processes, particularly after the formation of the interconnection structure
11
. As a result of this additional flow in the BPSG layer
9
, the interconnector
11
on the BPSG layer
9
will tend to migrate in a direction (alternative directions of movement indicated by arrows) towards a metal electrode
14
, thereby causing an electrical short between the interconnector
11
and the metal electrodes
14
. This migration of the interconnector
11
is more prevalent in peripheral areas that have a low pattern density than in cell areas that have a high pattern density.
The conventional semiconductor device having the configuration described above in which an electrical short occurs between the interconnector and the metal electrodes due to the incomplete reflow of the BPSG layer at the initial manufacturing stage, is undesirable in terms of the reliability and yield of the semiconductor device. In addition, it is known that electrical shorts between the interconnector and the metal electrodes caused by flowing of the BPSG layer, cannot be completely prevented even when the BPSG layer is reflowed at a temperature of 820° C. or more during the initial manufacturing stage.
One solution to the creation of electrical short between the interconnector layer and the metal electrodes is the formation of insulating spacers on the sidewalls of contact holes. This method, however, is inefficient in terms of the manufacturing time and cost because it requires the performance of additional process steps to form the insulating spacers.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for forming semiconductor devices in which occurrence of an electrical short between interconnectors and metal electrodes, due to flowing of a BPSG layer, can be prevented or significantly suppressed.
The objective of the present invention is achieved by a semiconductor device manufacturing method including: forming a transistor in a semiconductor substrate; depositing a first interlevel dielectric film to cover the transistor on the semiconductor substrate; depositing a BPSG layer as a planarization layer on the first interlevel dielectric film; reflowing the BPSG layer; etching the BPSG layer by using Ar ion sputtering until a portion of the first interlevel dielectric film is exposed, wherein the surfaces of the first interlevel dielectric film including the BPSG layer are planarized; forming an interconnector on the exposed portion of the first interlevel dielectric film; depositing a second interlevel dielectric film to cover the interconnection layer on the first interlevel dielectric film and the BPSG layer; and forming metal electrodes on the second interlevel dielectric film, the metal electrodes extending through the dielectric layers to contact predetermined regions of the transistor.
REFERENCES:
patent: 5668036 (1997-09-01), Sune
patent: 5899749 (1999-05-01), Becker et al.
patent: 6207987 (2001-03-01), Tottor
Dang Phuc T.
Hynix / Semiconductor Inc.
Nelms David
Pillsbury & Winthrop LLP
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