Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

2004-01-05

2004-12-14

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S614000, C438S928000, C438S977000, C438S667000

Reexamination Certificate

active

06831000

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a method of manufacturing a semiconductor device having through wirings that make possible electrical conduction between connection terminals on an element forming surface side and connection terminals on a back surface side.
2. Description of the Related Art
In reply to a request for a higher density of the packaging technology, the packaging structure in which a plurality of semiconductor chips are laminated and packaged three- dimensionally on the wiring substrate is developed nowadays. As the method of implementing such packaging structure, there is the method of connecting the connection terminals on the element forming surface side of the semiconductor chip and the connection terminals on the back surface side via the through holes that pass through the semiconductor chip and then laminating plural times this semiconductor chip on the wiring substrate to be connected mutually.
In the method of forming the through wirings in the semiconductor chip in the related art, as shown in
FIG. 1A
, first a semiconductor wafer
100
on which predetermined transistors, multi-layered wirings (not shown), etc. are formed and which has a thickness of about 400 &mgr;m is prepared. Connecting pads
102
are exposed from an upper surface of the semiconductor wafer
100
, and portions except the connecting pads
102
are covered with a passivation film
104
.
Then, as shown in
FIG. 1B
, a resist film (not shown) having opening portions at center portions of the connecting pads
102
is patterned on the connecting pads
102
and the passivation film
104
(masking step
1
).
Then, the connecting pads
102
and the underlying semiconductor wafer
100
are etched sequentially by RIE (Reactive Ion Etching), or the like while using the resist film as a mask. Thus, through holes
100
a
each passing through the semiconductor wafer
100
from the element forming surface to the back surface are formed.
Then, as shown in
FIG. 1C
, an insulating film
106
such as a silicon oxide film, or the like is formed on inner surfaces of the through holes
100
a
, the connecting pads
102
, and the passivation film
104
by the CVD, or the like. This insulating film
106
is formed to isolate electrically a conductive film, which is filled in the through holes
100
a
later, from the semiconductor wafer
100
.
Then, as similarly shown in
FIG. 1C
, a dry-film resist film
108
having opening portions
108
a
at portions, which correspond to major portions of the connecting pads
102
formed like a ring, is formed on the insulating film
106
(masking step
2
). Then, the insulating film
106
is etched by using the dry-film resist film
108
as a mask, and then the dry-film resist film
108
is removed. Thus, as shown in
FIG. 1D
, the insulating film
106
is still left on the inner surfaces of the through holes
100
a
, but the ring-like connecting pads
102
are exposed.
Then, as shown in
FIG. 1E
, a seed Cu film
110
is formed on the resultant structure in.
FIG. 1D
by the electroless plating, the sputter method, or the like. Then, a resist film
112
having opening portions
112
a
on the through holes
100
a
and the connecting pads
102
is formed (masking step
3
).
Then, a Cu film pattern
114
is formed in interiors of the through holes
100
a
and the opening portions
112
a
of the resist film
112
by the electroplating utilizing the seed Cu film
110
as a plating power-supply layer. Then, as shown in
FIG. 1F
, the resist film
112
is removed, and then the seed Cu film
110
is etched by using the Cu film pattern
114
as a mask. Thus, Cu bumps
114
a
each connected electrically to the connecting pad
102
and Cu plugs
114
b
each connected to this Cu bump
114
a
are formed.
Then, as shown in
FIG. 1G
, a thickness of the semiconductor wafer
100
is reduced by grinding the back surface of the semiconductor wafer
100
by virtue of the grinder. At this time, the semiconductor wafer
100
and the Cu plugs
114
b
filled in the through holes
100
a
are ground at the same time. Thus, top end portions of the Cu plugs
114
b
on the back surface side of the semiconductor wafer
100
act as connection terminals
114
c
on the back surface side. In this manner, the connecting pads
102
and the Cu bumps
114
a
connected thereto on the element forming surface side of the semiconductor wafer
100
are connected to the connection terminals
114
c
on the back surface side via the through holes
100
a.
Then, individual semiconductor chips are obtained by dicing the semiconductor wafer
100
.
Also, it is set forth in Patent Literature 1 (Patent Application Publication (KOKAI) Sho 59-222954), Patent Literature 2 (Patent Application Publication (KOKAI) Sho 63-156348), Patent Literature 3 (Patent Application Publication (KOKAI) Sho 61-88546), and Patent Literature 4 (Patent Application Publication (KOKAI) 2000-286304), for example, that in order to laminate and package a plurality of semiconductor chips three-dimensionally, the through wirings used to connect the connection terminals on the element forming surface side and the connection terminals on the back surface side are provided in the semiconductor chip.
However, in the above manufacturing methods in the related art, since three masking steps (masking steps
1
to
3
) are needed, not only the process becomes complicated to lower the yield of production but also there is a possibility that an increase in a production cost is brought about. Also, since the through holes and the Cu bumps are formed via individual masking steps respectively, the care must be taken not to cause the displacement in respective masking steps. Therefore, in case formations of the bumps, the connecting pads, and the through holes having above structures should be further miniaturized, in some cases it becomes difficult to get their desired structures because of the displacement.
In addition, in the above related art, upon grinding the back surface of the semiconductor wafer
100
, the Cu plugs
114
b
filled in the through holes
100
a
and the semiconductor wafer
100
must be ground simultaneously.
At this time, sometimes the Cu plugs
114
b
are electrically short-circuited mutually because the Cu plugs
114
b
to be ground are extended to the ground surface of the semiconductor wafer
100
, otherwise the grinding operation cannot be carried out satisfactorily because ground Cu pieces are clogged in the grinding wheel (grindstone) of the grinder. In this way, since the special grinding equipment is required of the related art, a huge plant and equipment investment must be made and thus it is possible to bring about an increase in a production cost.
Here, in above Patent Literatures 1, 2, 3 and 4, the above problems caused in manufacturing the semiconductor chip, which is equipped with the connecting pads and the through wirings connected to the bumps, are not taken into consideration at all.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method capable of manufacturing a thin semiconductor device having a structure, in which connection terminals on an element forming surface side and connection terminals on a back surface side are connected mutually via through holes respectively, without generation of any trouble.
The present invention provides a semiconductor device manufacturing method which comprises the steps of preparing a semiconductor substrate having a connecting pad on an element forming surface; forming a seed metal film to cover the connecting pad on the semiconductor substrate; forming a bump metal film as a pattern having an opening portion in a predetermined portion on an area of the seed metal film that corresponds to the connecting pad; forming a through hole, which is communicated with the opening portion of the bump metal film and passes through to a back surface of the semiconductor substrate, by etching sequentially the see

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