Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

1999-11-17

2004-08-03

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S589000, C438S981000, C438S258000, C438S264000

Reexamination Certificate

active

06770550

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an MOS structure (a structure having a channel region selectively formed in the main surface of a semiconductor substrate, a set of source/drain regions selectively formed in the main surface of the semiconductor substrate with the channel region therebetween, and a gate electrode facing the channel region through a gate insulating film), and particularly to an improvement for compatibly realizing reduction in leakage current and increase in gate insulating film reliability.
2. Description of the Background Art
FIGS. 55 and 56
are manufacturing process diagrams showing a conventional method for manufacturing a semiconductor device having the MOS structure, i.e., an insulated-gate semiconductor device. Particularly, this semiconductor device is constructed as an MOS transistor. In this specification, according to the common usage in this field of art, “MOS transistor” and “MOS structure” generally also include those having gate electrodes formed of conductors other than metal.
FIG. 55
is a front section of an intermediate structure obtained before formation of the gate electrode and
FIG. 56
is a front section of an intermediate structure obtained after formation of the gate electrode. In the process shown in
FIG. 55
, first, an STI (Shallow Trench Isolation)
102
is formed in the main surface of the semiconductor substrate
101
. The STI
102
is formed by selectively forming a trench having a depth of about 0.2 to 0.3 &mgr;m in the main surface of the semiconductor substrate
101
and then burying an insulating film in the trench. The STI
102
is formed to separate a set of adjacent elements. In this specification, STI as a structure and STI as an element isolation method are both represented as “STI.”
Subsequently, a well implantation and a channel-cut implantation are performed to form a well layer and a channel-cut layer in the semiconductor substrate
101
.
FIG. 55
does not show the well layer and the channel-cut layer.
Next, a gate insulating film
103
is formed on the main surface of the semiconductor substrate
101
. The gate insulating film
103
is formed as a silicon oxide film by performing a thermal oxidation in an H
2
O atmosphere, O
2
atmosphere, N
2
O atmosphere, NO atmosphere, or NO/O
2
atmosphere, for example. The gate insulating film
103
may be formed by depositing a high-dielectric-constant film such as Ta
2
O
5
. The gate insulating film
103
usually has a thickness of about 1.5 to 8 nm, though it depends on the rated value of the power-supply voltage.
Deposited next on the gate insulating film
103
are a film of polysilicon
104
doped with phosphorus at a concentration of 5×10
20
/cm
3
and having a thickness of 0.1 &mgr;m, a WSix (tungsten silicon compound; x=2, 3) film
105
having a thickness of 0.1 &mgr;m, and an insulating film
106
having a thickness of 0.05 &mgr;m, in this order. These films are deposited by using CVD (Chemical Vapor Deposition). The gate electrode is formed later from the two-layer structure of the polysilicon film
104
and the WSix film
105
. In other cases, the gate electrode may be formed by using a metal material, such as W and Co, in place of the polysilicon/WSix two-layer structure.
Next, resist (photoresist) is applied on the insulating film
106
and then the resist is patterned by a transfer process to form a resist
107
. The insulating film
106
is deposited on the WSix film
105
for the purpose of preventing halation, specifically, to prevent the phenomenon in which the resist
107
is finished in smaller size than the transferred mask due to reflecting light from the layer underlying the resist in the transfer process. The insulating film
106
can serve to prevent halation because the insulating film
106
has a smaller reflectance than the WSix film
105
.
Next, the process shown in
FIG. 56
is performed. In the process of
FIG. 56
, first, an anisotropic etching is performed by using the resist
107
as a mask to selectively remove the insulating film
106
, the WSix film
105
, and the polysilicon film
104
. As a result, the gate electrode
110
is formed as a two-layer structure having the polysilicon film
104
and the WSix film
105
. Reactive ion etching (RIE) is used as the anisotropic etching for forming the gate electrode
110
.
After that, impurity ions are selectively implanted into the main surface of the semiconductor substrate
101
by using the gate electrode
110
and the insulating film
106
thereon as masks. As a result, in the main surface of the semiconductor substrate
101
, source/drain layers (the generic name of the source layer and the drain layer)
111
are formed in the source/drain regions (the generic name of the source region and the drain region)
109
opposing through the channel region
108
right under the gate electrode
110
.
In the conventional MOS transistor, the gate electrode
110
and the source/drain layers
111
are formed as described above. For example, when the MOS transistor is of n-channel type, the conductivity type of the channel region
108
is p type and the conductivity type of the source/drain layers
111
is n type.
As shown in
FIG. 56
, in the anisotropic etching process for forming the gate electrode
110
, the polysilicon film
104
, the WSix film
105
, and the insulating film
106
are selectively removed in the areas located above the source/drain regions
109
and the STI
102
. In this process, the resist
107
used as a mask is etched away, too. In the anisotropic etching, over etching is implemented to prevent the resist
107
from partially remaining unremoved.
When the over etch starts, the insulating film
106
, the WSix film
105
, and the polysilicon film
104
located above the source/drain regions
109
have been already removed by etching, with only the insulating films
103
b
remaining. While the resist
107
is mainly etched in the over etching, part of the insulating film
106
and part of the gate insulating films
103
b
are etched, too. Accordingly, the insulating films
103
b
on the source/drain regions
109
become thinner than the gate insulating film
103
a
on the channel region
108
.
In reactive ion etching, CF
4
becomes radicals in the form of CFx (x=1, 2, 3) in a plasma, and then they are accelerated by electric field in the ion sheath and transported to the surface of the WSix
105
and polysilicon film
104
, which form the gate electrode
110
. Then the radicals cut the bonds of W—Si, Si—Si, etc. and remove silicon components and tungsten components in the form of SiF
2
, WF
2
, etc.
At the same time, the radicals accelerated in the electric field and energized enter the oxide film, silicon, etc. for about 10 nm depth at the maximum. Then, as the insulating films
103
b
become thinner, the following phenomena become more serious: the radicals (CFx) enter the main surface of the semiconductor substrate
101
to form levels (i.e., donor or acceptor levels), radiation damage (damage caused by radiation) occurs in the main surface of the semiconductor substrate
101
and the gate insulating film, and W atoms (or ions) emitted from the WSix
105
by sputtering enter the main surface of the semiconductor substrate
101
to form levels. The damaged layers
112
shown in
FIG. 56
represent the radiation-damaged and level-formed layers in the main surface of the semiconductor substrate
101
.
While most of the radiation damage is annealed out (eliminated by annealing) in thermal treatment process performed later in a nitrogen atmosphere, C, W, and the like remain near the main surface of the semiconductor substrate
101
. When these levels are covered by a depletion layer, then SRH (Shockley-Read-Hall) current and TAT (Trap Assisted Tunnel) current increase, both of which cause leakage current in gate-off state. According to simulation, it is known that the electric field strength is as high as 5×10
5
V/cm or more in the gate end regions

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