Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

1998-09-30

2003-05-13

Chaudhuri, Olik (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S471000

Reexamination Certificate

active

06562733

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing device, and particularly to a method of removing heavy metal impurities when MOS transistor is formed on a silicon wafer.
2. Description of the Related Art
In a process of manufacturing semiconductor devices, the surface and the inside of silicon wafer are contaminated with impurities of heavy metal in some cases. The contamination occurs in a high-temperature heat treatment step, an ion implantation step, an etching step, etc. It is known that if impurities of heavy metal are segregated into a silicon oxide film, reliability of the insulation characteristics represented by TDDB (Time Dependent Dielectric Breakdown) characteristic, etc. is degraded.
A gettering technique is known as one of methods of preventing degradation of the reliability of oxide films due to heavy metal impurities. According to this technique, heavy metal which is included in silicon wafer is removed from the sub-surface of the wafer and captured so that the heavy metal is not taken into a gate oxide film when the gate oxide film is formed on the surface of the wafer. For example, as described in “ULSI Process Control Engineering” (written by Hideki Tsuya and issued in 1995 by Maruzen), various methods have been proposed for the gettering technique.
The following are four representative methods for the gettering technique. A first method is a PBS (Polysilicon Back Sealing) method in which a polysilicon film is deposited on the back surface of the wafer, a second method is a phosphorus diffusion method in which high-concentration phosphorus is diffused from the back surface of the wafer, a third method is an IG (Internal Gettering) method of using crystal defects which occur due to oxygen precipitates in a Czochralski grown silicon wafer, and a fourth method is a p/p
+
epitaxial wafer method in which a high-concentration boron layer is used as a gettering layer. According to these gettering methods, heavy metal is captured by diffusing the heavy metal from the sub-surface of wafer in which MOS transistors are formed to the gettering layer at the inside or the back side of the wafer, whereby the contamination amount of the heavy metal in the wafer sub-surface is reduced. Thereafter, a gate oxide film is formed, so that the contamination amount of heavy metal to be taken into the oxide film can be reduced.
However, when the thickness of the gate oxide film is reduced due to microstructure of MOS transistors, even contamination of low-concentration heavy metal degrades the reliability of the oxide film. Such cases have been reported by Y. Shiramizu, M. Tanaka, S. Yamasaki, M. Nakamori, N. Aoto and H. Kitajima in “Ext. Abst. of Solid State Devices and Materials” (1996) 362-364, and by W. B. Henley, L. Jastrzebski and N. F. Haddad in “Journal of Non-crystalline Solids” 187(1995) 134-139. This shows that the reduction of the heavy metal impurity concentration in the wafer sub-surface by the conventional gettering techniques is insufficient to thin gate oxide films.
Further, it is Necessary to form shallow junction for advanced ULSIs. Therefore, the low temperature processes and the rapid thermal processes are required so that impurities to form p-type and n-type semiconductor regions are little diffused. This means that diffusion of the impurities of heavy metal hardly occurs. As a result, heavy metal is hardly diffused to the gettering layer at the inside or the back surface of the wafer, so that the gettering process does not progress.
SUMMARY OF THE INVENTION
The present invention has been implemented to overcome the above problem, and has an object to provide a semiconductor device manufacturing method which can form a thin gate oxide film having high reliability in fabricating MOS transistors on a silicon wafer, so that the yield is enhanced in a process of manufacturing LSIs which are designed in enhanced microstructure and highly integrated, and reliability of transistors are enhanced.
A semiconductor device manufacturing method according to a first aspect of the present invention comprises a step of subjecting silicon wafer to a heat treatment in an oxidation furnace to form a first silicon oxide film, a step of gradually cooling the silicon wafer having the first silicon oxide film formed thereon and then taking out the silicon wafer from the oxidation furnace, and a step of removing the first silicon oxide film on the silicon wafer and then forming a gate silicon oxide film. Particularly, the cooling temperature in the cooling step is set to 800° C. or less.
A semiconductor device manufacturing method according to a second aspect of the present invention comprises a step of subjecting silicon wafer to a heat treatment in an oxidation furnace to form a first silicon oxide film, a step of keeping the silicon wafer at a low temperature for a fixed time after the silicon wafer having the first silicon oxide film formed thereon is cooled, and then taking out the silicon wafer from the oxidation furnace, and a step of removing the first silicon oxide film on the silicon wafer and then forming a gate silicon oxide film. Particularly, the temperature at which the silicon wafer is kept for the fixed time is set to 800° C. or less.
When the silicon wafer is thermally oxidized, heavy metal impurities which are solid-solved in the wafer surface layer portion have such properties that they are segregated in a silicon oxide film or at the Si/SiO
2
interface.
FIG. 7
is a graph showing a measurement result of iron (Fe) concentration in SIMS (Secondary Ion Mass Spectroscopy) after the silicon wafer which is beforehand contaminated with Fe is thermally oxidized at 850° C. As shown in
FIG. 7
, the concentration of Fe is higher in the silicon oxide film and at the Si/SiO
2
interface. 10
15
cm
−3
is the detection limitation concentration of SIMS. In this example, the Fe concentration is set to a relatively high value. If the Fe concentration is reduced, it would be difficult to directly detect the heavy metal impurities by SIMS because the precision is insufficient, however, the same phenomenon also occurs even in the case where the Fe concentration is low. When this phenomenon occurs in the process of forming the gate silicon oxide film, the reliability of the gate silicon oxide film is degraded.
The present invention positively uses this phenomenon. The concentration of the heavy metal impurities in the wafer sub-surface is reduced before the gate silicon oxide film is formed so that the segregation of the heavy metal impurities into the gate silicon oxide film constituting the MOS transistor is suppressed. Therefore, as described with reference to the conventional technique, the heavy metal impurities existing in the wafer sub-surface are captured as much as possible by the gettering layer according to any one of the PBS method, the phosphorus diffusion method, the IG method and the p/p
+
epitaxial method. Nevertheless, some amount of heavy metal remains in the wafer sub-surface. When the thickness of the gate silicon oxide film is reduced, the residual heavy metal impurities cannot be neglected. Therefore, a step of forming a silicon oxide film (thermally-oxidized film) before the gate silicon oxide film is formed is added. In this step, the heavy metal existing in the wafer surface layer portion is taken into the silicon oxide film as much as possible. The heavy metal thus taken is removed together with the silicon oxide film. Thereafter, the wafer is cleaned and then the gate silicon oxide film is formed. At this time, the heavy metal in the wafer sub-surface is reduced at maximum, so that the gate silicon oxide film having high reliability can be obtained.
In the present invention, the following method is used so that as much an amount of heavy metal as possible can be taken into the Si/SiO
2
interface. According to a first method, after the silicon oxide film is formed, the wafer having the silicon oxide film is gradually cooled to a low temperature. According to a s

Affiliated with

Also associated with

Rating

Semiconductor device manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device manufacturing method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3064078