Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-08-31
2002-07-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S638000, C438S640000, C438S678000
Reexamination Certificate
active
06420261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a semiconductor device manufacturing method including the step of forming wiring layers of a multilevel wiring structure and a via by using a dual damascene method.
2. Description of the Prior Art
In recent years, the width of the wiring is narrowed with the miniaturization of the semiconductor device and also the distance between the wirings becomes narrower. Therefore, wiring resistance is increased and also a parasitic capacitance due to the wirings is increased. This delays a signal speed and prevents a higher speed operation of the semiconductor device according to the scaling law.
Under such circumstances, in order to reduce the parasitic capacitance between the wirings and the wiring resistance, it is needed to check again the multilevel wiring forming method and the insulating material and the metal wiring material.
The insulating material with the small dielectric constant is effective to reduce the wiring capacitance. Also, selection of the metal wiring material is shifted from aluminum (Al) to copper (Cu) having the small resistivity to reduce the wiring resistance.
Because it is difficult to apply the conventional dry etching in working a copper film, the damascene method is employed to work the copper film. The damascene method can be roughly classified into the single damascene method and the dual damascene method.
According to the single damascene method, formation of the plug (via) used to connect the underlying wiring and the overlying wiring and formation of the wirings must be conducted by individual steps. According to the dual damascene method, the wirings and the plug can be formed simultaneously.
The multilayer structure of the wiring layers of the semiconductor device is advanced with the miniaturization. For example, the number of wirings comes up to six layers in the semiconductor device of 0.18 &mgr;m wiring width generation. In this case, the wiring structure can be formed by repeating similar steps twelve times (six wiring formation steps and six plug formation steps), for example, according to the single damascene method, whereas the wiring structure can be formed only by repeating similar steps six times according to the dual damascene method.
The reason why the number of steps employed in the dual damascene method is merely half of the single damascene method is that, as described above, the wirings and the plug can be formed simultaneously. Hence, the dual damascene method is advantageous to suppress a production cost and to increase a production efficiency.
In addition, since the contact resistance between the underlying wiring and the plug connected to this wiring is low if the dual damascene method is employed, a failure in contact between them can be avoided easily and reliability of the wiring can be enhanced.
The dual damascene method is set forth in, for example, Patent Application Publication (KOKAI) Hei 9-55429 and Patent Application Publication (KOKAI) Hei 10-112503 in which the dual damascene method is applied to the interlayer insulating film including the low dielectric constant insulating film.
To begin with, steps of forming the copper plug and the copper wiring structure by the dual damascene method which is set forth in Patent Application Publication (KOKAI) Hei 9-55429 are shown in
FIGS. 1A
to
1
D.
First, as shown in
FIG. 1A
, a first silicon oxide film
2
, an organic low dielectric constant film
3
, and a second silicon oxide film
4
are formed in sequence on a silicon substrate
1
. In this case, fluorocarbon polymer such as polytetrafluoroethylene is employed as material of the organic low dielectric constant film. Then, an opening
4
a
having a wiring profile is formed in the second silicon oxide film
4
by patterning the second silicon oxide film
4
. Then, as shown in
FIG. 1B
, resist is formed on the second silicon oxide film
4
and the opening
4
a
. A plug window
5
a
is formed on a part of the opening
4
a
by exposing/developing the resist. The resultant resist is employed as a resist pattern
5
. Then, as shown in
FIG. 1C
, a via-hole
6
is formed by etching the organic low dielectric constant film
3
and the first silicon oxide film
2
in sequence through the plug window
5
a
of the resist pattern
5
. Then, as shown in
FIG. 1D
, a wiring recess
7
is formed by selectively etching the organic low dielectric constant film
3
by the oxygen plasma through the opening
4
a
of the second silicon oxide film
4
. Then, although not particularly shown, copper is buried in the via-hole
6
and the wiring recess
7
, whereby the plug and the wiring are formed at the same time.
Next, steps of forming the copper plug and the copper wiring structure by the dual damascene method which is set forth in Patent Application Publication (KOKAI) Hei 10-112503 are shown in
FIGS. 2A
to
2
C.
First, as shown in
FIG. 2A
, wiring recesses are formed in a silicon oxide film
12
formed on a semiconductor substrate
11
, and then underlying wirings
13
are buried in the recesses. Then, a low dielectric constant resin film
14
and a first photoresist film
15
with low sensitivity are formed in sequence on the silicon oxide film
12
and the underlying wirings
13
. Then, a hole latent image
15
a
in the first photoresist film
15
is formed by exposing. Then, a second photoresist film
16
with high sensitivity is coated on the first resist film
15
. A latent image
16
a
of a wiring is then formed by exposing the second photoresist film
16
. A part of the wiring latent image
16
a
is formed to overlap with the hole latent image
15
a
. Then, as shown in
FIG. 2B
, the first photoresist film
15
and the second photoresist film
16
are developed successively, so that the wiring latent image
16
a
is removed to form a wiring window
16
b
and also the hole latent image
15
a
is removed to form a hole window
15
b
. After this, the first photoresist film
15
, the second photoresist film
16
, and the low dielectric constant resin film
14
are etched sequentially from the upper side, as shown in FIG.
2
C. As a result, a vertical contact hole
17
and a wiring recess
18
are formed in the low dielectric constant resin film
14
. The copper (not shown) is buried in the vertical contact hole
17
and the wiring recess
18
simultaneously. Such copper is used as the plug in the vertical contact hole
17
and also used as the wiring in the wiring recess
18
.
The above prior arts have a few problems as follows.
In the steps as shown in
FIG. 1A
, when the photoresist
8
used for a patterning mask is removed by the oxygen plasma, the organic low dielectric constant film
3
made of hydrocarbon resin under the second silicon oxide film
4
is etched into a wiring profile by the oxygen plasma. Therefore, pattern precision of the via-hole formed in the second silicon oxide film
4
is degraded. This is because chemical properties of the low dielectric constant organic material containing the hydrocarbon approximate the photoresist
8
and thus only the photoresist
8
cannot be removed selectively.
In this case, the reason why the hydrocarbon resin is employed as the organic low dielectric constant film is that the hydrocarbon resin is superior to the fluorocarbon polymer in adhesiveness for the silicon oxide film.
In addition, in the steps shown in
FIGS. 2A
to
2
C, three different resin materials of the low dielectric constant resin film
14
, the first photoresist film
15
, and the second photoresist film
16
must be etched at the same etching rate. However, respective etching rates of these resin materials are different depending upon the width of the wiring recess
18
and the diameter of the vertical contact hole
17
. Therefore, if the wiring recesses each having a different profile or width, or the vertical contact holes
17
each having a different diameter are to be formed in the same layer, it is difficult to etch these resin materials while contro
Armstrong Westerman & Hattori, LLP
Berry Renee R
Fujitsu Limited
Nelms David
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