Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
1999-03-09
2001-04-24
Whitehead, Jr., Carl (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S384000, C438S233000
Reexamination Certificate
active
06221728
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a mixture of a MOSFET and a low-resistance resistive element, which enables the manufacture of a low-resistance resistive element without an increase in the resistance of the FET gate electrode and diffusion layer.
2. Description of the Related Art
In a circuit that transfers high-speed signals, if the characteristic impedance of the signal transmission line is not matched to the load impedance, the signal will be reflected, resulting in waveform distortion. Even between LSI devices, in order to transfer high-speed signals, it is necessary to provide impedance matching so that unwanted reflections do not occur. In recent years, with advances in multifunctional LSI devices, there has been an increased need to build into an LSI device a termination resistance for the purpose of establishing impedance matching. The termination resistance is a resistance of approximately 50, and it is important that this resistance be of high accuracy. If variations occur in the termination resistance, the establishment of impedance matching becomes impossible, so that the LSI fails to function. In the case of forming a termination resistance element within an LSI device, the problem is to limit the variation in the resistance value. Additionally, with the shrinking of semiconductor feature size, it has become possible to achieve high speeds. However, along with these advances in microfine device technology siliciding of the gate electrode and diffusion layer has been used as a method of limiting an increase in parasitic resistances of the gate electrode and diffusion layer. The smaller device features become, the lower becomes the resistance of silicide to heat, leading to the appearance of an increase in resistance cause by coagulation.
A method of manufacturing a semiconductor device in which a MOS transistor such as in the past is combined with a termination resistance element is described below, with reference being made to
FIGS. 2
(
a
) through (
d
).
As shown in
FIG. 2
(
a
), onto a silicon substrate
21
is formed an element separation oxide film
22
of approximately 400 nm, a gate oxide film
23
of approximately 5 to 10 nm, and a gate electrode
24
of approximately 150 to 200 nm, after which a side wall is formed on the gate electrode and after ion implantation, thermal processing is performed to form a diffusion layer
25
, these elements being formed by known technologies, resulting in the formation of a MOS transistor.
Next, as shown in
FIG. 2
(
b
) a sputtering method is used to form titanium to a thickness of approximately 30 to 50 nm, and RTA (rapid thermal annealing) is performed at approximately 700° C., so as to form titanium silicide
26
on the diffusion layer. Then, the unreacted titanium is removed.
Next, as shown if
FIG. 2
(
c
), a CVD oxide film
27
is formed to a thickness of approximately 100 to 200 nm, and a tungsten silicide
28
, which will serve as a resistive element, is sputtered onto the CVD oxide film
27
to a thickness of approximately 100 to 200 nm. Additionally, a photolithography process and anisotropic etching are used to pattern the tungsten silicide
28
.
Next, as shown in
FIG. 2
(
d
), an interlayer insulation film
29
is formed to a thickness of approximately 1000 nm, after which a contact hole
30
is formed, and thermal processing (RTA) is performed at approximately 750 to 800° C. in order to lower the resistance of the tungsten silicide, because of low temperature of approximately 750 to 800° C.
Then, an aluminum electrode is formed.
Because in the above-noted manufacturing method tungsten silicide is formed after titanium siliciding over the gate electrode and the diffusion layer, it is not possible to achieve a low enough resistance in the tungsten silicide. Additionally, it is difficult to limit the variation in the resistance value that is required for building a termination resistance inside of an LSI device to within 10%. In order to achieve a sufficiently low tungsten silicide resistance and limit variation therein, it is necessary to perform thermal processing, for approximately 20 minutes if done at 700° C. and for approximately 1 minute if done at 800° C. However, because of the low thermal resistance of titanium silicide, if this type of thermal processing is performed after the formation of the titanium silicide, the titanium silicide will coagulate, resulting in an increase in the resistance. That is, the resistance of the gate electrode and the diffusion layer will increase, and the performance of the transistor will suffer. The above-describe method, therefore, is not a suitable method for the formation of a termination resistance that is required to be a low resistance value and also have high accuracy, which is why there has been a need for the development of a method of forming a low-resistance termination resistance.
Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which there is a mixture of a MOSFET and a low-resistance resistive element, and which enables the manufacture of a low-resistance resistive element having high accuracy, without an increase in the resistance of the FET gate electrode and diffusion layer.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention has the following described basic technical constitution.
Specifically, a first aspect of a semiconductor manufacturing method according to the present invention is a method of manufacturing a semiconductor device which has a mixture of a MOSFET and a low-resistance resistive element that is made of tungsten silicide film, wherein etching is done of said tungsten silicide film, which will serve as the resistive element, to a prescribed shape, after which thermal processing for the purpose of activating a diffusion layer of said MOSFET is performed, thereby reducing the resistance of said tungsten silicide film to a low resistance.
In a second aspect of the present invention is a method comprising: a first step of forming a first oxide film after forming a gate electrode, a second step of forming said tungsten silicide film on said first oxide film, and a third step of depositing a second oxide film on said tungsten silicide film.
In a third aspect of the present invention, in the step of etching the tungsten silicide film into a prescribed shape, the tungsten silicide film is etched using the second oxide film as a mask, and the second oxide film is left remaining on the tungsten silicide.
The fourth aspect of the present invention includes: a first step of forming an element separation film on a semiconductor substrate and further forming a gate oxide film and a gate electrode thereon, a second step of forming an oxide film on the semiconductor substrate including the gate electrode, forming a tungsten silicide film on this first oxide film, and forming a second oxide film on this tungsten silicide film, a third step of etching the second oxide film, a fourth step of etching the tungsten silicide film, which will serve as a resistive element, using the second oxide film as a mask, a fifth step of etching the first oxide film using the second oxide film as a mask, a sixth step of performing ion implantation into a region that will become the source and the drain diffusion layer of the MOSFET and then performing thermal processing to achieve activation, and a seventh step of growing titanium over the entire surface and then forming titanium silicide film over the gate electrode and source and drain diffusion region.
In the fifth aspect, in the fourth step, the tungsten silicide film is etched with the second oxide film as a mask, and the second oxide film is left remaining on the tungsten silicide film.
In the sixth aspect, in the fifth step, by etching the first oxide film, a side wall of the gate electrode formed by this first oxide
Brewster William M.
Jr. Carl Whitehead
NEC Corporation
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