Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2006-11-14
2006-11-14
Luu, Chuong Anh (Department: 2818)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S527000, C438S530000, C438S257000, C438S595000
Reexamination Certificate
active
07135393
ABSTRACT:
A gate electrode is formed above an n-type well including an n-type threshold voltage adjustment region, ions of p-type impurity are implanted with a low acceleration energy to form extension regions in the n-type well on both sides of the gate electrode, side wall spacers are formed on the side walls of the gate electrode, ions of p-type impurity are implanted with a small dose causing substantially no abnormal tailing in the gate electrode and with a relatively high acceleration energy to form p-type source/drain regions deeper than the threshold adjustment region, ions of atoms are implanted into the semiconductor substrate to change the upper parts of the gate electrode and the source/drain regions to amorphous state, ions of p-type impurity are implanted with a large dose to form high-concentration parts in the source/drain regions, and the impurities introduced by the ion implantation are activated.
REFERENCES:
patent: 5976923 (1999-11-01), Tung
patent: 6569742 (2003-05-01), Taniguchi et al.
patent: 6894353 (2005-05-01), Samavedam et al.
patent: 6908837 (2005-06-01), Taniguchi et al.
patent: 7041549 (2006-05-01), Ootsuka
patent: 2005/0230781 (2005-10-01), Ema et al.
patent: 2006/0113627 (2006-06-01), Chen et al.
patent: 62-120082 (1987-06-01), None
patent: 4-283966 (1992-10-01), None
patent: 9-23003 (1997-01-01), None
patent: 9-260649 (1997-10-01), None
patent: 10-22503 (1998-01-01), None
patent: 11-186188 (1999-07-01), None
Atsushi Hori et al., High Speed 0.1 μm Dual Gate CMOS with Low Energy Phosphorus/boron Implantation and Cobalt Salicide, pp. 575-578, IEDM 1996.
Fujitsu Limited
Luu Chuong Anh
Westerman, Hattori, Daniels & Adrian , LLP.
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