Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-08-15
2002-11-12
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S203000, C365S225700
Reexamination Certificate
active
06480430
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device in which initial settings are made by use of internal fuses or the like.
2. Description of the Related Art
In semiconductor devices such as semiconductor memory devices, fuses of the fuse circuit provided in the devices are selectively disconnected to make settings with respect to address redundancy, input/output interface configurations, refresh cycles, etc., at the time of shipping out from the factory. In order to refer to the fuse information at the time of actual operation, semiconductor devices may employ one of two methods, i.e., either continuously applying electric currents to fuses so as to obtain the fuse information constantly or referring to the fuse information by use of a starter signal (i.e., internal reset signal) generated at the start of device operations and making initial settings to internal circuits based on the obtained fuse information.
The former method has a drawback in that the larger the number of fuses, the greater the electric current consumption. The latter method has an advantage in that the current consumption can be reduced because an electric current does not run through the fuses during actual operations, but has a problem in that timing of an internal reset signal generated at the start of device operations may differ from device to device because of product variation. Due to this product variation, an initial setting operation may be performed on an internal circuit before an internal power supply voltage rises to a sufficient level. In such a case, some transistors of the internal circuit may not receive sufficient power supply voltages, so that resulting settings may be different from the expected initial settings, possibly causing a malfunction.
Accordingly, there is a need for a semiconductor device that can make correct initial settings to internal circuits by referring to fuse information at the start of device operations.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a semiconductor device, including a fuse circuit which stores information represented by fuse connections, a power-on circuit which generates a power-on signal that changes a signal level thereof following power-on of the device, a timing circuit which starts a time measurement upon the signal level change of the power-on signal, and a control circuit which makes an initial setting by referring to the information of the fuse circuit in response to a completion of the time measurement for a predetermined duration.
In one embodiment, the timing circuit described above includes an oscillator and a counter. Further, the semiconductor device includes a memory cell array which stores information therein, and a refresh circuit which controls a refresh operation of the memory cell array, wherein the oscillator and the counter are the oscillator and the counter that are used by the refresh circuit to time a refresh cycle.
In the semiconductor device of the present invention as described above, an oscillator starts an operation thereof in response to the power-on signal generated at the time of device power-on, and a predetermined internal is timed based on the oscillating signal of the oscillator. After the passage of the predetermined interval, fuse information is referred to so as to make initial settings to a refresh cycle, redundancy processing, etc. In this manner, the timing at which the fuse information is referred to is not determined from the power-on signal as in the related-art configurations, but is determined by a predetermined interval that is timed by the timing device such as an oscillator. Because of this, even if the timing of the power-on signal generated at the start of device operations differs from device to device due to product variation, the present invention can avoid a troublesome situation in which the initial settings are made before the internal power supply voltage rises to a sufficient level. As a result, the present invention can avoid a malfunction that would otherwise be caused by wrong settings that are different from correct initial settings. Here, the predetermined interval that should pass before the start of an operation referring to the fuse information is such an interval as a stable circuit operation is guaranteed after a sufficient rise of the power supply voltage.
REFERENCES:
patent: 6201733 (2001-03-01), Hiraki et al.
patent: 6269051 (2001-07-01), Funaba et al.
patent: 6411169 (2002-06-01), Yabe et al.
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Nguyen Hien
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