Patent
1989-06-05
1990-12-25
James, Andrew J.
357 49, 357 55, H01L 2704
Patent
active
049807480
ABSTRACT:
In a semiconductor device having trench-shaped element isolating regions formed in a semiconductor body and also a conductive layer extending on each element isolating region and connected to an impurity diffusion region of the semiconductor body, there is formed an insulator layer region between an extension of the conductive layer and the element isolating region, and the insulator layer region is buried in the surface portion of the semiconductor body. In such construction, the insulation space between the conductive layer and the semiconductor body can be increased while the distance between the element isolating region and the impurity diffusion region can be shortened to consequently diminish the parasitic capacitance between the conductive layer and the semiconductor body, hence attaining a faster operation in the semiconductor device. When the present invention is applied to a bipolar transistor integrated circuit, a superfast operation is ensured due to the reduction of the base-to-collector capacitance.
REFERENCES:
patent: 4466177 (1984-08-01), Chao
patent: 4470024 (1984-09-01), Leuenberger
patent: 4609934 (1986-09-01), Haskell
patent: 4688069 (1987-08-01), Joy et al.
patent: 4799099 (1989-01-01), Verret et al.
Kemlage, "Multiple Depth Dielectric Isolation from a Single mask", Sept., 1979, IBM Technical Disclosure Bulletin, vol. 22, No. 4.
Hozumi Hiroki
Kayanuma Akio
Miwa Hiroyuki
Nakamura Minoru
Bowers Courtney A.
James Andrew J.
Sony Corporation
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