Semiconductor device layout method and layout program

Details Semiconductor device layout method and layout program Semiconductor device layout method and layout program

2007-08-23

2010-02-16

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07665053

ABSTRACT:
It is an aspect of the embodiments discussed herein to provide a semiconductor device layout method and a semiconductor device layout program that enable the minimum necessary decoupling capacitances to be placed efficiently according to a circuit configuration, placement positions, operation timings, and clock tree of functional circuits.

REFERENCES:
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patent: 2005/0251775 (2005-11-01), Wood
patent: 2006/0031795 (2006-02-01), Rahmat et al.
patent: 2008/0052654 (2008-02-01), Rahmat et al.
patent: 2008/0203494 (2008-08-01), Secareanu et al.
patent: 2002-288253 (2002-10-01), None
patent: 2004-055954 (2004-02-01), None
patent: 2006-040962 (2006-02-01), None
Bernstein et al., automated translation of Japanese Patent Document No. 2002-288253 A, machine translated on Jul. 5, 2009, 24 pages.
Kazuki, automated translation of Japanese Patent Document No. 2006-040962 A, machine translated on Jul. 5, 2009, 9 pages.

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