Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-30
2003-09-30
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06629303
ABSTRACT:
The invention relates to semiconductor device layouts and in particular to methods of laying out and manufacturing a semiconductor device having an arrangement of cells each surrounded by perimeter regions.
The cost of silicon wafers is high as is the cost of processing such semiconductor wafers to produce the final devices. The term “real estate” is used to describe the area of a semiconductor wafer, a term which accurately reflects the high cost of each small area. Accordingly, any technique that can increase the utilization of the wafer by increasing the number of devices on a single semiconductor wafer is extremely useful. There is an ongoing need to provide the maximum number of dies on a wafer.
One prior art approach is that described in U.S. Pat. No. 5,340,772 which suggests using unusual die shapes such as trapezoids and triangles, or even highly elongated rectangles. These are said to be able to be laid out more “efficiently” on a silicon wafer. However, the approach provides a large perimeter area as a fraction of wafer area. In some cases, such as those proposed in U.S. Pat. No. 5,340,772, an enlarged perimeter area may well be beneficial. For example, an enlarged perimeter may be useful where many inputs or outputs are required. However, the approach is by no means of universal application since the large perimeter can represent a waste of space in applications with a small number of inputs and outputs. Moreover, U.S. Pat. No. 5,340,772 does not teach a method of reducing the area of each individual die.
The structure of a double diode having two epitaxial diodes separated by a trough is illustrated in
FIG. 1. A
first diode
26
and a second diode
28
are electrically isolated and silicon dioxide
20
is deposited at the edge of the first
26
and second
28
diodes. A glass passivation layer
22
surrounds and fills the gap between the diodes. Such diodes are fabricated on a wafer having an array of diodes, which are split from one another by scribing. To permit this, a scribe region
24
is provided around the perimeter of the double diode structure.
Such a double diode has no requirement for a large number of bonding pads around its periphery. Accordingly, it would be wasteful to increase the size of the periphery. Nevertheless, there remains a need for this semiconductor device structure to be manufactured in such a way as to increase the number of double diodes per wafer. Similar considerations apply to other multiple-element semiconductor device structures.
According to the invention, there is provided a method of manufacturing a semiconductor device having an arrangement of cells and perimeter regions surrounding the cells, the perimeter regions between adjacent cells being common to the adjacent cells, the method including the steps of: determining the required width or widths of the perimeter regions; calculating an optimal aspect ratio of each cell to substantially minimize the total area of an arrangement of cells subject to the determined width or widths of the perimeter regions; and making a semiconductor device having an arrangement of cells separated by perimeter regions with widths as determined, the cells having an aspect ratio substantially in accordance with the calculated ratio.
In this way the total area of a semiconductor device according to the invention may be minimised. It is thus generally possible to fit a greater number of semiconductor devices on a single wafer of given size.
The aspect ratio may be within 20 percent, preferably 10 percent of the optimized aspect ratio. This small possible variation in aspect ratio may be needed having regard to other considerations, such as the perimeter characteristics, whilst still gaining the benefits of the invention. However, it is preferable for the chosen aspect ratio to be within 5 percent of the optimal aspect ratio to optimise the utilization of area.
The cells may be the active regions of the semiconductor device. The perimeter regions may be electrically less active regions of the device, or even electrically inactive regions, for example isolation or insulation regions. In one particular example, the cells may be diodes of a multiple-diode device. In another particular example, they may be emitter and/or base regions of a power transistor, and/or device cells of a cellular power device. Indeed, the layout principles of the present invention may be applied to a wide variety of device types, including integrated circuits.
The semiconductor device may have an n by m array of cells, where n and m are predetermined positive integers with n at least two. n may be unequal to m. The cells may be rectangular. Alternatively, any other cell shapes could also be used: in such cases the array need not be a simple n by m array but can be more complex if required to fit the cells efficiently within the device.
Preferably, n may be unequal to m and the smaller of n and m less than or equal to 10.
The semiconductor device may have n active areas or cells in an x direction and m active areas or cells in a y direction. Normally, especially for rectangular cells x and y are perpendicular. However, with other shapes of cells, the array may have basis vectors x and y that are not perpendicular. This may occur, for example, for parallelogram shaped cells.
The aspect ratio A
r
of width to length of the cells for orthogonal arrays may be calculated using the equation
A
r
=
mw
2
+
1
2
m
(
n
-
1
)
w
3
nh
2
+
1
2
n
(
m
-
1
)
h
3
wherein
h
2
is the predetermined width between the upper and lower cells and the edge of the die in the y direction;
w
2
is the predetermined width between the left and right cells and the edge of the die in the x direction;
h
3
is the predetermined width between adjacent cells in the y direction; and
w
3
is the predetermined width between adjacent cells in the x direction. The derivation of this equation will be explained below.
The width of the perimeter regions may be predetermined by the shape of the device and the design rules of the process being used. The required width of the inner perimeter regions arranged between cells may be different from the required width of the outer perimeter regions around the outside of the array. In particular, a scribe region may be provided around the outer periphery of the array to allow the individual semiconductor device to be separated from its neighbors on a wafer. Thus, the width of the outer perimeter region may need to be larger than the width of the inner perimeter regions by the required width of this scribe region.
The semiconductor device may be a double diode. The diode may have active epitaxial diode regions surrounded by passivation regions including glass passivation in a trench. As well as double diodes, other multiple mesa diode devices using such glass in trough passivation may be made.
Alternatively, the device may be an integrated circuit with circuit islands separated by isolation regions, for example of opposite conductivity type that extend through an epitaxial layer to define active-area islands of the integrated circuit.
Alternatively, the device may be, for example a cellular power transistor.
The semiconductor device may be a complete device that will be separated from its neighbours to form a die. Alternatively, the semiconductor device may form part of an integrated circuit. As will be appreciated, the reduction in area obtained by the invention is useful in either case.
In another aspect, the invention relates to a semiconductor device comprising an n by m array of cells, n and m being unequal positive integers with the smaller of n and m less than or equal to 10; and a plurality of perimeter regions of predetermined width or widths surrounding the cells, the perimeter regions between adjacent cells being common to the adjacent cells; wherein the aspect ratio of the cells is within 10 percent of the aspect ratio that minimizes the total area of the array subject to the constraint of the predetermined perimeter width or widths.
The width of the exterior perimeter region around the outs
Hardy David F. D.
Peake Steven T.
Koninklijke Philips Electronics , N.V.
Niebling John F.
Slobod Jack D.
Whitmore Stacy
LandOfFree
Semiconductor device layout does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device layout will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3064780