Semiconductor device interconnection structure

Details Semiconductor device interconnection structure Semiconductor device interconnection structure

1999-05-26

2001-11-13

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S773000, C257S774000, C257S758000

Reexamination Certificate

active

06316836

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an interconnection structure between conductors in a semiconductor device for effectively reducing contact resistance between the conductors in the interconnection structure.
(b) Description of the Related Art
In a conventional semiconductor device having various conductors overlying a semiconductor substrate, a via hole is generally formed penetrating through a dielectric film for electrically connecting a plurality of conductive layers together.
Examples of an interconnection structure between conductive layers in a conventional semiconductor device are shown in
FIGS. 1A
,
1
B,
2
A and
2
B.
FIG. 1A
is a top plan view of an interconnection structure and
FIG. 1B
is a sectional view of the structure of
FIG. 1A
taken along a line A—A. Similarly,
FIG. 2A
is a top plan view of another interconnection structure and
FIG. 2B
is a sectional view of the structure of
FIG. 2A
taken along a line A—A.
As shown in
FIG. 1B
, a silicon oxide film
16
is formed on a semiconductor substrate
17
and first layer conductors
11
are formed on the silicon oxide film
16
. A dielectric film
12
is then formed on the first layer conductors
11
. After the dielectric film
12
is flattened by employing a chemical mechanical polishing (CMP) technique, a via hole
18
is formed in the dielectric film
12
for connecting the first layer conductors
11
and second layer conductor
15
. The aperture size of the via hole
18
is made smaller than the area formed by overlap between the first layer conductor and the second layer conductor
11
,
15
as shown in
FIG. 1A
in order to secure the interconnection therebetween, The whole surface of the dielectric film
12
including the via hole
18
is coated with a conductive material
14
by employing a chemical vapor deposition (CVD) technique, and the top surface of the conductive material
14
is aligned with the top surface of the dielectric film
12
by employing a dry etching technique to fill the via hole
18
with the conductive material
14
to make the via plug. After this procedure, the second layer conductor
15
is formed on the via plug
18
.
As shown in
FIG. 2B
, a silicon oxide film
26
is formed on a semiconductor substrate
27
and two first layer conductors
21
are separately formed on the silicon oxide film
26
. A dielectric film
22
is then formed on the first layer conductors
21
and on the silicon oxide film
26
. Via holes
28
are formed smaller than an area formed by overlap between the first layer conductor
21
and a second layer conductor
25
. The via holes
28
are filled with a conductive material
24
and the second layer conductor
25
is formed on the via plugs
28
and the dielectric film
22
.
The width of conductors is generally made smaller and smaller in order to decrease the parasitic capacitance of the conductors for responding to a recent demand of high operational speed. Since the above decrease makes, an area formed by overlap between the first layer conductor and the second layer conductor smaller to reduce the aperture area, a contact resistance between the first layer conductor and the conductive material filled in the via hole increases. When a barrier metal layer is formed in the via hole by means of sputtering, a thickness of the barrier metal layer,at the bottom of the via hole is thinner than desired because the aperture area of the via hole is small so that the scattering of the contact resistance between the barrier metal layer in the via plug and the first layer conductor becomes larger. Since, further, the via hole is smaller than an area formed by overlapping between the first and the second layer conductors, the high accuracy of position adjustment between a mask for forming the via hole and the first layer conductor is required.
In order to solve this problem, a structure shown in
FIGS. 3A
to
3
C is proposed (JP-A-09(1997)-17868).
FIG. 3A
is a top plan view of the structure, and
FIGS. 3B and 3C
, are sectional views taken along the lines A—A and B—B, respectively, of FIG.
3
A.
As shown in
FIG. 3B
, a silicon oxide film
36
is formed on a semiconductor substrate
37
and a first layer conductor
31
is formed on the central part of the silicon oxide film
36
. A dielectric film
32
is then formed on the first layer conductor
31
and on the silicon oxide film
36
. A via hole
39
is formed in the dielectric film
32
for connecting the first layer conductor
31
and a second layer conductor
35
. This via hole
39
is made larger than an area formed by overlapping between the first and the second layer conductors
31
,
35
as shown in FIG.
3
A. The second layer conductor
35
is so formed that it is in contact with the first layer conductor
31
through the via hole
39
.
However, in this interconnection structure between the conductors, an unnecessary trench is formed between the dielectric film
32
and the second layer conductor
35
as shown in
FIG. 3C
so that coverage of the upper layers becomes worse. When two or more first layer conductors are present as shown in
FIG. 2B
, the same number of via holes as that of the first layer conductors are required. If the via hole shown in
FIG. 3B
is formed in
FIG. 2B
, further unnecessary trenches are produced.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device having an interconnection structure for preventing an increase of or a scattering of a contact resistance between conductors connected through a via hole formed in a dielectric film.
Another object of the present invention is to provide a semiconductor device having an interconnection structure which moderates an accuracy of position adjustment at the time of via hole formation.
A further object of the present invention is to provide a semiconductor device having an interconnection structure which eliminates unnecessary trenches generated in the via hole.
A still further object of the present invention is to provide a semiconductor device having an interconnection structure which elevates a coverage of upper layers.
The present invention provides a semiconductor device comprising: a substrate, a first dielectric film overlying said substrate, a first layer conductor formed on said first dielectric film, a second dielectric film formed on said first dielectric film and on said first layer conductor, a second layer conductor formed on said second dielectric film, said first layer conductor and said second layer conductor being electrically connected through at least one via hole formed in said second dielectric film, said via hole having a width larger than that of the first layer conductor and not larger than that of the second layer conductor, said via plug being entirely covered with said second layer conductor.
In accordance with the present invention, an increase of and a scattering of contact resistance between a first (lower) layer conductor and a second (upper) layer conductor in an interconnection structure in a semiconductor device can be reduced by making an aperture area of a via hole larger. Further, an accuracy of position adjustment between a mask for forming a via hole and the first layer conductor may be moderated. Since an unnecessary difference in level can be eliminated by covering the via plug by means of the upper layer conductor, step coverage of the upper layer conductor is increased. Moreover, the scattering of the contact resistance between the upper and the lower layer conductors can be further reduced by connecting a plurality of the lower layer conductors with the upper layer conductor through a single via hole.
The above and other objects, features and advantages of the present invention will be more apparent from the following description referring to the accompanying drawings.


REFERENCES:
patent: 4916521 (1990-04-01), Yoshikawa et al.
patent: 5404046 (1995-04-01), Matsumoto et al.
patent: 5612574 (1997-03-01), Summerfelt et al.
patent: 5616959 (1997-04-01), Jeng
patent: 5616961 (19

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