Semiconductor device including signal generating circuit with le

Details Semiconductor device including signal generating circuit with le Semiconductor device including signal generating circuit with le

1994-04-18

1996-02-06

Nelms, David C.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518911, 36523006, 326106, 326108, 326121, G11C 800

Patent

active

054901197

ABSTRACT:
A semiconductor memory device includes a pull up circuit (811) for pulling up a potential of a first node (812), a pull down circuit (813) for pulling down the potential of the first node, an inverter circuit (814b) having its input connected to a first input node (814a) connected to the first node (812) and its output connected to a first output node (814c) and operating with a boosted potential Vpp, and a p channel MOS transistor (814d) connected between a boosted potential node (50c) and the first input node (814a), with its gate electrode connected to the first output node (814c). The memory device provides a signal having a higher level than the supply potential with smaller area of layout.

REFERENCES:
patent: 4506164 (1985-03-01), Higuchi
patent: 4782247 (1988-11-01), Yoshida
patent: 4926070 (1990-05-01), Tanaka
patent: 4958091 (1990-09-01), Roberts
patent: 5039882 (1991-08-01), Arakawa
patent: 5051959 (1991-09-01), Nakano
patent: 5136541 (1992-08-01), Arakawa
patent: 5214606 (1993-05-01), Hashimoto
patent: 5289417 (1994-02-01), Ooshi
patent: 5351217 (1994-09-01), Jeon

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