Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-10-09
2003-08-26
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S516000, C257S541000
Reexamination Certificate
active
06611042
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates a semiconductor device in which a plurality of resistors having the same characteristics are formed on an element isolation layer at a high accuracy while suppressing variations of the respective characteristics.
BACKGROUND OF THE INVENTION
In a conventional semiconductor device, as shown in
FIG. 17
, the surface of a silicon substrate
1
is selectively oxidized to obtain a field oxide film
3
a
serving as a dioxide silicon layer. This region has been used as a region for element isolation.
However, with micropatterning of elements in recent years, an element isolation layer called an STI (Shallow Trench Isolation) which can be designed to be accurate has been used. The outline of a method of manufacturing the STI is shown in
FIG. 18A
to FIG.
18
F.
As shown in
FIG. 18A
to
FIG. 18F
, a protective film
2
is stacked on a silicon substrate
1
shown in
FIG. 18A
(FIG.
18
B). The protective film
2
is selectively etched to obtain a structure in FIG.
18
C. Etching is performed by using the protective film
2
as a mask to form a trench in the silicon substrate
1
as shown in FIG.
18
D. Subsequently, a silicon oxide film
3
is deposited by plasma CVD or the like to obtain a structure shown in FIG.
18
E. Finally, the resultant structure is subjected to a polishing process such as CMP (Chemical Mechanical Polish) to obtain a structure shown in FIG.
18
F.
Even though an element isolation region obtained by the field oxide film
3
a
is an isolation region having a wide area as shown in
FIG. 17
, a structure in which the thickness of the central portion and the thickness of the peripheral portion are almost equal to each other is difficult to obtain because of the nature of the manufacturing method. In contrast to this, since the element isolation layer region obtained by the STI is subjected to the polishing process such as the CMP, a relatively wide area (e.g., 10 &mgr;m×10 &mgr;m or more) has a characteristic structure in which the central portion is thinner than, i.e., dented relative to, the peripheral portion.
However, in such an element isolation region obtained by the STI, a new problem which is not posed in a conventional field oxide film has been posed. More specifically, when a plurality of resistors having the same characteristics are to be formed on an element isolation layer region having a relatively wide area, as shown in FIG.
19
A and
FIG. 19B
, focus is offset by the positions of the resistors in a photolithographic operation because of the dent described above. Therefore, the resistors vary in size, and it is difficult to form a plurality of resistors having the same characteristics with a high accuracy.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device in which a plurality of resistors having the same characteristics are formed at a high accuracy on an element isolation layer region formed by a polishing process such as STI.
According to the semiconductor device of one aspect of the present invention, a plurality of resistors having the same characteristics are formed on an element isolation layer, at least one diffusion region exists between one resistor and a resistor adjacent thereto, and the plurality of resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal to each other.
According to the semiconductor device of another aspect of the present invention, a plurality of resistors having the same characteristics are formed on an element isolation layer, at least one metal wiring layer exists between one resistor and a resistor adjacent thereto, and the plurality of resistors and the metal wiring layers are arranged such that all distances between the resistors and the metal wiring layers around the corresponding resistors are equal to each other.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 5498899 (1996-03-01), Palara
patent: 5500553 (1996-03-01), Ikegami
patent: 5567977 (1996-10-01), Jimenez
patent: 2001/0030364 (2001-10-01), Katon
patent: 2002/0014672 (2002-02-01), Noble et al.
patent: 08-279608 (1996-10-01), None
patent: 10-189879 (1998-07-01), None
Haruhana Hideyo
Uneme Yutaka
Yamamoto Seiji
Cao Phat X.
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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