Semiconductor device including output buffer and control...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

Reexamination Certificate

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Details

C326S029000, C327S170000

Reexamination Certificate

active

07952383

ABSTRACT:
There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance.

REFERENCES:
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5898321 (1999-04-01), Ilkbahar et al.
patent: 6288563 (2001-09-01), Muljono et al.
patent: 6384621 (2002-05-01), Gibbs et al.
patent: 7038486 (2006-05-01), Aoyama et al.
patent: 7-86900 (1995-03-01), None
patent: 8-97693 (1996-04-01), None

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