Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2011-05-31
2011-05-31
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S029000, C327S170000
Reexamination Certificate
active
07952383
ABSTRACT:
There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance.
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Cho James
Elpida Memory Inc.
McGinn IP Law Group PLLC
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