Semiconductor device including multiple field effect...

Details Semiconductor device including multiple field effect... Semiconductor device including multiple field effect...

1998-03-11

2003-04-01

Chaudhuri, Olik (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S392000

Reexamination Certificate

active

06541823

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods thereof, and more particularly, to a semiconductor device including a plurality of field effect transistors and a manufacturing method thereof.
2. Description of the Background Art
In recent years, as semiconductor devices came to be more densely integrated and reduced in size, 2-power supply devices having external voltage of a conventional level and internal voltage of a lower level have been proposed.
FIG. 79
is a cross sectional view showing such a conventional 2-power supply semiconductor device including a plurality of field effect transistors.
Referring to
FIG. 79
, the conventional 2-power supply semiconductor device include a first field effect transistor supplied with first power supply voltage (low Vdd) and a second field effect transistor supplied with second power supply voltage (high Vdd) higher than low Vdd formed on a main surface of a p type semiconductor substrate
101
and spaced apart from each other. An isolation oxide film
102
is formed between the first and second field effect transistors.
In the low Vdd region, a pair of first source/drain regions
110
and a pair of low concentration impurity diffusion regions
108
are formed spaced apart from each other on the main surface of semiconductor substrate
101
having a first channel region therebetween. Low concentration, n type impurity diffusion region
108
formed adjacent to the first channel region and high concentration, n type impurity diffusion region
110
formed adjacent to n type impurity diffusion region
108
constitute an LDD (Lightly Doped Drain) structure. A first gate insulating film
106
is formed on the first channel region. A first gate electrode
118
is formed on first gate insulating film
106
. A sidewall oxide film
109
is formed on a side of first gate electrode
118
. The first field effect transistor supplied with low Vdd is formed of first source/drain regions
110
, impurity diffusion regions
108
, first gate insulating film
106
, and first gate electrode
118
.
In the high Vdd region, a pair of second source/drain regions
117
and a pair of low concentration impurity diffusion regions
116
are formed on the main surface of semiconductor substrate
101
, spaced apart from each other and having a second channel region therebetween. Second source/drain region
117
and low concentration impurity diffusion region
116
, in other words low concentration n type impurity diffusion region
116
formed adjacent to the second channel region and high concentration, n type impurity diffusion region
117
formed adjacent to n type impurity diffusion region
116
constitute an LDD structure. A second gate insulating film
104
is formed on the second channel region. First gate insulating film
106
is formed on second gate insulating film
104
. A second gate electrode
119
is formed on first gate insulating film
106
. A sidewall oxide film
120
is formed on a side of second gate electrode
119
. Second source/drain regions
117
and impurity diffusion region
116
, second gate insulating film
104
, first gate insulating film
106
and first gate electrode
119
form the second field effect transistor supplied with high Vdd. The gate insulating films
104
and
106
of the second field effect transistor supplied with high Vdd should be thicker than the first gate insulating film
106
of first field effect transistor supplied with low Vdd.
Referring to
FIGS. 80
to
86
, a method of manufacturing the conventional 2-power supply semiconductor device will be now described.
Isolation oxide film
102
is formed on the main surface of semiconductor substrate
101
to surround an active region. Second gate insulating film
104
is formed on the active region on the main surface of semiconductor substrate
101
. A resist pattern
105
a
is formed on second gate insulating film
104
positioned in the high Vdd region and on isolation oxide film
102
. The structure as shown in
FIG. 80
is thus obtained.
An isotropic etching is performed using resist pattern
105
a
as a mask to remove second gate insulating film
104
positioned in the low Vdd region to obtain the structure as shown in FIG.
81
. Resist pattern
105
a
is then removed.
As shown in
FIG. 82
, first gate insulating film
106
is formed on the main surface of semiconductor substrate
101
and on second gate insulating film
104
.
A first doped polysilicon film
103
(see
FIG. 83
) is deposited on first gate insulating film
106
and isolation oxide film
102
. Resist patterns
105
b
and
105
c
are formed on the regions of first doped polysilicon film
103
to be first and second gate electrodes
118
and
119
(see FIG.
79
). The structure as shown in
FIG. 83
is thus obtained.
Then, using resist patterns
105
b
and
105
c
as masks, an anisotropic etching is performed to remove a part of first doped polysilicon film
103
, and first and second gate electrodes
118
and
119
are formed as a result. Resist patterns
105
b
and
105
c
are then removed. The structure as shown in
FIG. 84
is thus obtained. The gate insulating film portion of the second field effect transistor formed of first and second gate insulating films
106
and
104
can be made thicker than the first gate insulating film
106
of the first field effect transistor. Thus, the breakdown voltage of the second field effect transistor can be greater than the breakdown voltage of the first field effect transistor, so that the second field effect transistor may be supplied with voltage higher than the first field effect transistor.
As shown in
FIG. 85
, an n type impurity is introduced into a prescribed region of the main surface of semiconductor substrate
101
to form low concentration n type impurity diffusion regions
108
and
116
.
Sidewall oxide films
109
and
120
(see
FIG. 86
) are formed on sides of first and second gate electrodes
118
and
119
. An n type impurity is then introduced into a prescribed region of the main surface of semiconductor substrate
101
to form high concentration n type impurity diffusion regions
110
and
117
as shown in FIG.
86
.
The conventional 2-power supply semiconductor device is manufactured as described above.
In the manufacture of the 2-power supply semiconductor device, resist pattern
105
a
is directly formed on second gate insulating film
104
positioned in the high Vdd region. In the following removal of resist pattern
105
a
, defects (local irregularities) are sometimes generated in the surface of second gate insulating film
104
. A light etching processing for removing resist pattern
105
a
is directly performed to the surface of second gate insulating film
104
, second gate insulating film
104
may be reduced in thickness. The defects in the surface of second gate insulating film
104
and the reduction in thickness lead to a reduction in the breakdown voltage of second gate insulating film
104
, and as a result electrical characteristics of the semiconductor device including the field effect transistor deteriorate.
As a countermeasure, a manufacturing method as shown in
FIGS. 87
to
93
has been proposed.
Referring to
FIGS. 87
to
93
, the proposed conventional method of manufacturing a 2-power supply semiconductor device including a plurality of field effect transistors will be described.
Isolation oxide film
102
is formed on the main surface of p type semiconductor substrate
101
to surround an active region. Second gate insulating film
104
is formed on the active region in the main surface of p type semiconductor substrate
101
. First doped polysilicon film
103
is formed on second gate insulating film
104
and isolation oxide film
102
. Resist pattern
105
a
is formed on the region of first doped polysilicon film
103
to be second gate electrode
119
(see
FIG. 88
) positioned in the high Vdd region to obtain the structure as shown in FIG.
87
.
An anisotropic etching is performed using resist pattern
105
a
as a m

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