Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2005-01-25
2005-01-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S051000, C365S063000
Reexamination Certificate
active
06847575
ABSTRACT:
In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
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Ayukawa Kazushige
Miura Seiji
Saitou Yoshikazu
Dinh Son T.
Mattingly Stanger & Malur, P.C.
Renesas Technology Corp.
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