Semiconductor device including impurity layer having...

Details Semiconductor device including impurity layer having... Semiconductor device including impurity layer having...

2001-03-15

2003-04-01

Chaudhuri, Olik (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C438S174000, C438S194000

Reexamination Certificate

active

06541825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a trench-type isolation structure and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor integrated circuit, in order to completely independently control elements in its operation, it is necessary to eliminate electrical interference between the elements. For this reason, an isolation structure having an isolation region is adopted in the semiconductor integrated circuit. As one of the isolation structures, a trench isolation method is widely known and various improvements thereof are proposed.
The trench isolation method is a method to electrically insulate the elements by forming a trench which extends from a surface of a substrate towards the inside thereof and filling the inside of the trench with a dielectric substance. In this method, there is little bird's beak, which is found in the isolation structure formed by the LOCOS method. For this reason, the isolation structure by the trench isolation method needs a smaller area on the surface of the substrate to form than that by the LOCOS method, and therefore the trench isolation method is a preferable method to promote size reduction of the semiconductor integrated circuit. Accordingly, the trench isolation method is an essential isolation method in the semiconductor integrated circuit whose size is to be further reduced in the future.
FIG. 23
is a schematic plan (top) view showing a semiconductor device
101
P in the background art.
FIGS. 24 and 25
are (vertical) cross sections taken along the line AP—AP and the line BP—BP in
FIG. 23
a
respectively.
FIG. 26
is an enlarged cross section showing part of FIG.
25
. In
FIG. 23
, part of the elements shown in
FIGS. 24
to
26
are omitted.
As shown in
FIGS. 23
to
26
, the semiconductor device
101
P comprises a P-type silicon single crystal substrate (hereinafter, referred to simply as “substrate”)
1
P. A trench
2
P is formed, extending from a main surface
1
SP of the substrate
1
P towards the inside of the substrate
1
P, and the trench
2
P forms an isolation region AR
2
P.
A silicon oxide film
9
AP is formed on an inner surface
2
SP of the trench
2
P and a silicon oxide film
9
BP is formed on the silicon oxide film
9
AP. In this case, the inside of the trench
2
P is filled with the silicon oxide films
9
AP and
9
BP (also generally referred to as “silicon oxide film
9
P”). The silicon oxide film
9
P is a so-called trench isolation.
In the background-art semiconductor device
101
P, the silicon oxide film
9
P which serves as the trench isolation has a shape sagging from the main surface
1
SP of the substrate
1
P along an opening edge of the trench
2
P (hereinafter, also referred to as “sag or depression”)
9
RP.
An N channel-type field effect transistor (NMOSFET) is formed in an active region AR
1
P of the semiconductor device
101
P. In more detail, a gate insulating film
4
P extends on the main surface
1
SP of the substrate
1
P across the active region AR
1
P (see FIG.
23
). A polysilicon film
5
AP and a tungsten silicide film
5
BP are layered on the gate insulating film
4
P in this order, and the polysilicon film
5
AP and the tungsten silicide film
5
BP form a gate electrode
5
P. Further, as shown in
FIGS. 25 and 26
, the gate electrode
5
P extends also on the silicon oxide film
9
P across the silicon oxide film
9
P and is also arranged in the sag
9
RP of the silicon oxide film
9
P. A sidewall oxide film
41
P is formed on the gate insulating film
4
P, being in contact with a side surface of the gate electrode
5
P.
Further, two source/drain layers
6
P are formed in the main surface
1
SP of the substrate
1
P with a channel region of the MOSFET below the gate electrode
5
P interposed therebetween. The source/drain layers
6
P consists of an N
+
-type layer
6
BP and an N
−
-type layer
6
AP, and the N
−
-type layer
6
AP has an impurity concentration lower than that of the N
+
-type layer
6
BP and is formed closer to the channel region.
Furthermore, a channel impurity layer
10
P to control a threshold voltage of the MOSFET is formed in the main surface
1
SP of the substrate
1
P. The channel impurity layer
10
P is formed of a P-type layer like the substrate
1
P and has an impurity concentration higher than that of the substrate
1
P. The channel impurity layer
10
P is provided in a region deeper than the channel region and the whole of it is formed in a plane substantially parallel to the main surface
1
SP of the substrate
1
P. Part of the channel impurity layer
10
P and part of the source/drain layers
6
P share a formation region (overlap one another) in the substrate
1
P, and more specifically, the channel impurity layer
10
P is formed across bottom portions of the source/drain layers
6
P.
Next, a method of manufacturing the semiconductor device
101
P will be discussed, referring to
FIGS. 27
to
31
along with
FIGS. 23
to
26
. Further,
FIGS. 27
to
31
are vertical cross sections taken along the line AP—AP of
FIG. 23
, like FIG.
24
.
First, the substrate
1
P is prepared, and the main surface
1
SP of the substrate
1
P is thermally oxidized to form a silicon oxide film
7
P (see FIG.
27
). Subsequently, a silicon nitride film
8
P (see
FIG. 27
) is formed on the silicon oxide film
7
P.
Next, a resist (not shown) to cover a region other than the region which is to be the isolation region is formed on the silicon nitride film
8
P by photolithography technique. Then, by anisotropic etching with the resist used as a mask, the silicon nitride film
8
P, the silicon oxide film
7
P and the sub
1
P is partially etched in this order. With this etching, a trench
2
aP is formed, extending from an exposed surface of the silicon nitride film
8
P to the inside of the substrate
1
P as shown in FIG.
27
. After that, the inner surface
2
SP of the trench
2
aP is thermally oxidized to form a silicon oxide film
9
AaP as shown in
FIG. 28
, and subsequently a silicon oxide film
9
BaP is so de posited as to cover the whole surface of the substrate
1
P on the side of the main surface
1
SP to fill the inside of the trench
2
aP by the HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) method.
The silicon oxide film
9
BaP is polished until the silicon nitride film
8
P is exposed by the CMP (Chemical Mechanical Polishing) method with the silicon nitride film
8
P used as a stopper (see FIG.
29
). With this polishing, the portion of the silicon oxide film
9
BaP existing in the trench
2
aP remains as the silicon oxide film
9
BbP.
Then, the silicon nitride film
8
P is removed with thermal phosphoric acid and subsequently the silicon oxide film
7
P is removed with hydrofluoric acid (see FIG.
30
). With these removing processes, the trench
2
P which is part of the trench
2
aP existing in the substrate
1
P remains. Further, as shown in
FIG. 30
, in the process using the hydrofluoric acid, the sag
9
RP is formed in the silicon oxide films
9
AaP and
9
BbP along an opening edge of the trench
2
P.
Next, the main surface
1
SP of the substrate
1
P is thermally oxidized to form a silicon oxide film again. Then, the channel impurity layer
10
P is formed by ion implantation as shown in FIG.
31
. Subsequently, the silicon oxide film is removed with the hydrofluoric acid. At this time, the silicon oxide films
9
AaP and
9
BbP is partially etched to form the silicon oxide film
9
P consisting of the silicon oxide films
9
AP and
9
BP, but the sag
9
RP is formed or enlarged in this process using the hydrofluoric acid.
After that, the silicon oxide film, the polysilicon film and the tungsten silicide film are sequentially formed and patterned to form the gate insulating film
4
P and the gate electrode
5
P (see FIGS.
24
and
25
). The ion implantation to form the N
−
-type layer
6
AP, formation of the sidewall oxide film
41
P and the ion implantation to form the N
+
-type layer
6
BP are sequentiall

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