Semiconductor device including gate wiring, main electrodes...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S335000, C257S342000, C257S343000

Reexamination Certificate

active

07576392

ABSTRACT:
A semiconductor device disclosed herein comprises a semiconductor layer which includes a first semiconductor region of a first conductivity type, a base region of a second conductivity type, and a plurality of second semiconductor regions of the first conductivity type; a gate wiring which is formed on the semiconductor layer via a first insulating film; a plurality of main electrodes which are electrically connected to the plurality of second semiconductor regions and which are insulated from the gate wiring, wherein the gate wiring is arranged between the main electrodes and upper surfaces of the main electrodes are higher than an upper surface of the uppermost layer of the gate wiring; and a connecting plate which is directly connected onto uppermost layers of the main electrodes.

REFERENCES:
patent: 6025646 (2000-02-01), Sakai et al.
patent: 6285058 (2001-09-01), Narazaki et al.
patent: 6316814 (2001-11-01), Nagata et al.
patent: 6342709 (2002-01-01), Sugawara et al.
patent: 6396127 (2002-05-01), Munoz et al.
patent: 6606120 (2003-08-01), Merrill et al.
patent: 6855957 (2005-02-01), Yamazaki et al.
patent: 6862070 (2005-03-01), Sugimoto et al.
patent: 6864508 (2005-03-01), Yamazaki et al.
patent: 2004/0026753 (2004-02-01), Matsuki et al.
patent: 2000-114445 (2000-04-01), None
patent: 2002-314018 (2002-10-01), None

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