Semiconductor device including gate electrode for applying...

Details Semiconductor device including gate electrode for applying... Semiconductor device including gate electrode for applying...

2011-06-14

2011-06-14

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S197000, C438S287000, C257SE21004, C257SE21058, C257SE21190, C257SE21278, C257SE21510

Reexamination Certificate

active

07960281

ABSTRACT:
A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

REFERENCES:
patent: 5155571 (1992-10-01), Wang et al.
patent: 5815223 (1998-09-01), Watanabe et al.
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6251778 (2001-06-01), Fang et al.
patent: 6342421 (2002-01-01), Mitani et al.
patent: 6495418 (2002-12-01), Shimizu et al.
patent: 6682965 (2004-01-01), Noguchi et al.
patent: 6750486 (2004-06-01), Sugawara et al.
patent: 6906393 (2005-06-01), Sayama et al.
patent: 7132317 (2006-11-01), Arao
patent: 7183204 (2007-02-01), Sayama et al.
patent: 7470618 (2008-12-01), Sayama et al.
patent: 4-99037 (1992-03-01), None
patent: 05-136075 (1993-06-01), None
patent: 9-199719 (1997-07-01), None
patent: 11-031665 (1999-02-01), None
patent: 11-204492 (1999-07-01), None
patent: 2000-058822 (2000-02-01), None
patent: 2001-257273 (2001-09-01), None
patent: 2001-284558 (2001-10-01), None
patent: 2002-93921 (2002-03-01), None
patent: 2002-329868 (2002-11-01), None
J. Welser, et al., “NMOS and PMOS Transistors Fabricated in Strained Silicon/Relaxed Silicon-Germanium Structures”, Proc. of International Electron Device Meeting 1992, IEDM 92, pp. 1000-1002.
T. Mizuno, et al., “High Performance Strained-Si p-MOSFETs on SiGe-On-Insulator Substrates Fabricated by Simox Technology”, Proc. of International Electron Device Meeting 1999, IEEE, pp. 934-936.

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