Semiconductor device including duty cycle correction circuit

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S149000, C365S206000

Reexamination Certificate

active

10758539

ABSTRACT:
A duty cycle correction (DCC) circuit receives first and second clock signals and outputs a duty cycle adjusted clock signal, and a control circuit detects a process variation and controls respective slew rates of the first and second clock signals based on the detected process variation. The DCC circuit may include a first inverter having an input that receives the first clock signal, a second inverter having an input that receives the second clock signal, a third inverter having an input commonly connected to outputs of the first and second inverters, a first variable capacitor connected between the input of the first inverter and a ground voltage, and a second variable capacitor connected between the input of the first inverter and the ground voltage. In this case, the respective capacitance values of the first and second variable capacitors are set by the control circuit.

REFERENCES:
patent: 5614855 (1997-03-01), Lee et al.
patent: 5845862 (1998-12-01), Cipriani
patent: 6320438 (2001-11-01), Arcus
patent: 6342800 (2002-01-01), Stark et al.
patent: 6570944 (2003-05-01), Best et al.
patent: 6643790 (2003-11-01), Yu et al.
patent: 2004/0075462 (2004-04-01), Kizer et al.
patent: 1020000043233 (2000-07-01), None
patent: PCT WO 01/71915 (2001-09-01), None

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