Semiconductor device including delay locked loop having...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S149000

Reexamination Certificate

active

07961018

ABSTRACT:
A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.

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patent: 2004-095155 (2004-03-01), None
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patent: 10-2001-0004224 (2001-01-01), None
patent: 10-2004-0020171 (2004-03-01), None
patent: 10-2007-0036561 (2007-04-01), None

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