Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-11-13
2003-11-18
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S592000, C438S586000, C438S587000, C438S588000, C257S413000
Reexamination Certificate
active
06649500
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and method for manufacturing the same, and more specifically to a semiconductor device including an insulated gate field effect transistor (IGFET) including a gate electrode that includes polysilicon and metal or metal silicide having a high melting point and a method of manufacturing the same.
BACKGROUND OF THE INVENTION
In order to improve the integration of a semiconductor device it is desirable to make smaller contact holes for a contact electrode to provide a connection between wiring layers and source/drain regions of a metal oxide semiconductor field effect transistor (MOSFET). It is also desirable to make the contact holes having improved accuracy of placement. In order to do this, a technique for forming a contact hole and electrode has been developed and is known as a self aligned contact (SAC).
Referring to
FIGS. 9 and 10
, cross-sectional views of a conventional manufacturing method of conventional semiconductor device having SAC technique after various processing steps are set forth.
Referring now to FIG.
9
(
a
), gate insulating film
202
consisting of silicon oxide (such as SiO
2
) is formed on the surface of silicon substrate
201
. A laminated film consists of poysilicon film
203
, WSi (tungsten silicide) film
204
, and a cap film
205
consisting of a silicon nitride (such as Si
3
N
4
) film. Using a photolithography technique, cap film
205
, WSi film
204
, and polysilicon film
203
are etched into a desired pattern to form gate electrode
200
.
In regions other than the gate electrode, the surface of gate insulating film
202
is also etched and made thinner. Thus, the film thickness of gate insulating film
202
is increased by thermal oxidation to replace the etched portions. As illustrated in FIG.
9
(
b
), during this step, a silicon oxide side wall film
207
is formed on the side surface of gate electrode
200
.
As illustrated in FIG.
9
(
c
), the surface of silicon substrate is subjected to ion implantion with an impurity to form source drain regions
208
with a self alignment method in which gate electrode
200
is used as a mask. In this way, a MOS type transistor is formed.
Referring now to FIG.
9
(
d
), silicon nitride film
209
is formed with a chemical vapor deposition (CVD) method. Silicon nitride film
209
serves as an etching stopper film.
Referring now to FIG.
10
(
a
), interlayer insulating film
210
such as a BPSG (Boro-PhosphoSilicate Glass) film is formed on the entire surface to cover gate electrode and provide a flat surface.
Referring to FIG.
10
(
b
), a hole
212
a
is opened in interlayer insulating film
210
over the source/drain region
208
using a photolithography technique. When forming hole
212
a
, etching stopper film
209
formed on the side surface of gate electrode
200
is not etched. Only interlayer insulating film
210
composed of BPSG is etched based on a difference of a selective etching ratio between etching stopper film
209
and interlayer insulating film
210
.
Referring now to FIG.
10
(
c
), an anisotropic etching is applied to etching stopper film
209
exposed in hole
201
a
. Further etching is applied to gate insulating film
202
. In this way, contact hole
212
is opened with a SAC technique.
Next, as illustrated in FIG.
10
(
d
), a wiring electrode
213
a
is formed in contact hole
212
to provide an electrical connection between a top part of wiring electrode
213
and source/drain region
208
. Because contact hole
212
is formed using a SAC technique with etching stopper film
209
on the side surface of gate electrode
200
, the MOS type element can be made fine. Even if a mask for opening a contact hole is out of position, side wall film
207
is not etched due to the etching stopper film
209
. Thus, upper layer electrode
204
and lower layer electrode
203
of gate electrode
200
can be prevented from being exposed in contact hole
212
. Thus, a margin for positioning the mask for the contact hole
212
can be increased and yield may be improved.
FIG. 11
are cross-sectional views of a conventional manufacturing method of conventional semiconductor device having SAC technique after various processing steps are set forth. FIG.
11
(
a
) illustrates a reduced distance between the stopper film
209
and the surface of the silicon substrate
201
in a region close to the edge of lower layer electrode
203
. FIG.
11
(
b
) illustrates an overhang in a side wall oxide layer. FIG.
11
(
c
) illustrates a void in a BPSG interlayer insulating film.
In the formation of a contact electrode using the conventional SAC technology, a thermal oxidation step is performed as illustrated in FIG.
9
(
b
). This thermal oxidation step is necessary because the gate insulating film
202
is partially etched and made thinner during the etching of cap film
205
, upper layer electrode
204
, and lower layer electrode
203
when forming the gate electrode
200
. If the silicon nitride film (stopper film
209
) is formed after the above-mentioned etching step without the additional thermal oxidation step, a distance between the stopper film
209
and the surface of the silicon substrate
201
in a region close to the edge of lower layer electrode
203
is reduced. This reduced distance is illustrated in FIG.
11
(
a
) as a reduced interval t. Hot carriers are likely to be trapped in an interface between the silicon nitride film (stopper film
209
) and the silicon oxide film (gate insulating film
202
). This can change the value of the threshold voltage of the MOS type transistor, thus making it difficult to manufacture a MOS type transistor in accordance to the designed values. To solve this problem, the thermal oxidation step is performed as illustrate in FIG.
9
(
b
) and the thickness of gate insulating film
202
is increased. This may prevent variations of the threshold value caused by hot carriers being trapped in the interface between the silicon nitride film (stopper film
209
) and the silicon oxide film (gate insulating film
202
) so that the desired characteristics of the MOS transistor can be achieved.
A technique of thermal oxidation including the side surface of the gate electrode has been proposed by the applicant and disclosed in Japanese Laid-Open Patent Publication No. 02-47871.
Thermal oxidation treatment for increasing the thickness of gate insulating film
202
causes side surfaces of the polysilicon film (lower layer electrode
203
) and the WSi film (upper layer electrode
204
) to be oxidized simultaneously. In this way, silicon oxide film (side wall film
207
) is formed as illustrated in FIG.
9
(
b
).
However, a silicide material, such as WSi (upper layer electrode
204
) may be more likely to be oxidized than polysilicon (lower layer electrode
203
) depending on the oxidation condition. Accordingly, depending upon the oxidation condition in the step illustrated in FIG.
9
(
b
), side wall film
207
may become thicker on the side surface of upper layer electrode
204
than on the side surface of lower layer electrode
203
as illustrated with side wall film
207
in FIG.
11
(
b
). In this case, side wall film
207
may include an overhang portion
207
a
that protrudes laterally from upper layer electrode
204
.
When there is an overhang portion
207
a
protruding from a side wall film
207
, the regions around the sides of gate electrode
200
are shielded during the ion implantation step as illustrated in FIG.
11
(
b
). This can prevent regions of the source/drain region
208
near the edges of the gate electrode
200
from being sufficiently ion implanted with an impurity. This can cause an increased diffusion layer resistance of the source/drain region
208
located in the vicinity of the gate electrode
200
and adversely affect characteristics of the MOS transistor.
Also, a side wall film
207
including an overhang portion
207
a
on the side surface of upper layer electrode
204
can cause the CVD silicon nitride film (etching stopper film
209
) in FIG.
9
(
d
) to include a pr
Cao Phat X.
Le Thao X.
NEC Corporation
Sako Bradley T.
Walker Darryl G.
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