Semiconductor device including a trench with at least one of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S328000, C257S329000, C257S332000, C257S510000

Reexamination Certificate

active

06710401

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for forming a trench MOS gate to be applied to a semiconductor device, particularly to a power device. The invention also relates to a device isolation technique.
2. Description of the Background Art
A. Background Art
(a-1) First Background Art and Problems Thereof
FIGS. 65
to
72
are cross-sectional views showing a conventional process for forming a trench MOS gate portion in step-by-step fashion. In particular,
FIG. 72
is a cross-sectional view when a trench MOS gate portion
131
has been formed.
Referring to
FIG. 65
, a doped P type region
2
is initially formed on an upper surface of a semiconductor substrate
1
made of Si and the like. A heavily doped N type region
3
is selectively formed in an upper surface of the doped P type region
2
. An oxide film
21
is formed on top of the structure thus obtained. Then a trench
4
is formed which extends through the oxide film
21
, the doped P type region
2
, and the heavily doped N type region
3
(FIG.
65
).
A silicon oxide film
7
is formed in the trench
4
(FIG.
66
). After the oxide films
7
and
21
are removed (FIG.
67
), a silicon oxide film is formed as a gate oxide film
9
(FIG.
68
).
An oxide film which is removed immediately after it is formed, such as the silicon oxide film
7
, is referred to as a “sacrificial oxide film” hereinafter. For shaping of the trench and removal of defects, strain and contamination in the trench, the sacrificial oxide film is sacrificed without remaining in a structure to be completed later. The silicon oxide film
7
of 100 to 300 nm in thickness is formed in an atmosphere of oxygen at a temperature ranging from 950 to 1100° C., for example.
The gate oxide film
9
is generally formed by thermal oxidation in an atmosphere of steam at a temperature not more than 1000° C. This is because the oxide film formed by thermal oxidation in an atmosphere of steam is, in general, less defective than the oxide film formed by thermal oxidation in an atmosphere of oxygen and because the oxide film is less defective at a lower temperature.
Low-resistance polycrystalline silicon
10
, for example, is filled into the trench
4
(
FIG. 69
) to form a gate electrode
22
in the trench
4
. A silicon oxide film
11
is formed on the gate electrode
22
(FIG.
70
). A CVD oxide film
12
is formed on top of the structure provided through the foregoing steps (
FIG. 71
) and is then shaped by etching into the trench MOS gate portion
131
(FIG.
72
).
The trench
4
after the silicon oxide film
7
is once formed and removed has a characteristic configuration as illustrated in FIG.
67
. That is, an opening portion and a bottom of the trench
4
are of angular configurations
5
c
and
6
c
, respectively.
Such configurations of the trench
4
result in a non-uniform thickness of the gate oxide film
9
formed in the trench
4
. In particular, the gate oxide film
9
is most pronouncedly thin in positions reflecting a configuration
5
d
of the opening portion of the trench
4
and a configuration
6
d
of the bottom of the trench
4
.
Such reduced thickness of the gate oxide film
9
in the trench
4
particularly in the opening portion and bottom of the trench
4
results in gate breakdown position and breakdown voltage failures. In addition, a leak current of the gate oxide film
9
increases.
Further, the angular configurations
5
c
,
6
c
of the trench
4
deteriorate the characteristics of the trench MOS gate portion
131
. In the step of forming the trench
4
, defects are prone to occur about the trench
4
. The defects deteriorate the characteristics of channels formed when a predetermined potential is applied to the gate electrode
22
, and reduces a mobility in an MOS gate channel which is a basic characteristic of a power device having the trench MOS gate portion
131
due to defects, strain and contamination adjacent an MOS gate interface, resulting in a rise in on state voltage.
(a-2) Second Background Art and Problems Thereof
FIGS. 73
to
81
are cross-sectional views showing a process for fabricating lateral IGBTs trench-isolated in an SOI (silicon on insulator) structure in step-by-step fashion.
Referring to
FIG. 73
, substrates
1
e
and
1
d
made of silicon and the like are bonded together, with a silicon oxide film
25
therebetween. P layers
41
and N
+
layers
42
are selectively formed in an upper portion of the semiconductor substrate
1
e
. A silicon oxide film
43
is formed over the semiconductor substrate
1
e.
The silicon oxide film
43
is selectively removed so that parts of the P layers
41
and N
+
layers
42
are exposed (FIG.
74
), and silicon etching is performed using the remaining silicon oxide film
43
as a mask. This permits the semiconductor substrate
1
e
to be selectively excavated down to form trenches
44
(FIG.
75
).
Then, sacrificial oxide films
45
are once selectively formed on inner walls of the trenches
44
by thermal oxidation (FIG.
76
), and the silicon oxide films are etched. This permits the removal of parts of the silicon oxide film
25
, all of the sacrificial oxide films
45
and all of the silicon oxide film
43
, and also permits the trenches
44
to be further excavated down to the level lower than the bottom of the semiconductor substrate
1
e
(FIG.
77
). Thermal oxidation in an atmosphere of steam at a temperature not more than 1000° C. provides isolation oxide films
46
around the remaining semiconductor substrate
1
e
(including the P layers
41
and N
+
layers
42
) (FIG.
78
).
Polycrystalline silicon
47
is deposited over the structure of
FIG. 78
to fill the trenches
44
with the polycrystalline silicon
47
(FIG.
79
). The polycrystalline silicon
47
over the semiconductor substrate
1
e
is selectively removed so that the polycrystalline silicon
47
remains only in the trenches
44
. The polycrystalline silicon
47
is covered with field oxide films
48
. The field oxide films
48
are also formed on the surface of the semiconductor substrate
1
e
between the P layers
41
and the N
+
layers
42
(FIG.
80
). Then a predetermined doped layer is formed, and lateral IGBTs are formed which are isolated from each other by isolating portions
13
a
having a trench structure (FIG.
81
).
Construction of the isolating portions
13
a
in this manner causes the problems of the thickness of the isolation oxide films
46
similar to the first background art problems. Specifically, as shown in
FIG. 78
, the semiconductor substrate
1
e
(including the P layers
41
and N
+
layers
42
) is of an angular configuration in opening portions
44
a
and bottoms
44
b
of the trenches
44
. The isolation oxide films
46
in these portions are pronouncedly thinner than those in other portions. The isolation oxide films
46
are prone to be broken particularly in the bottoms
44
b
. This causes the problem of a lowered isolation breakdown voltage by the isolating portions
13
a.
SUMMARY OF THE INVENTION
The present invention is intended for a method of fabricating a semiconductor device. According to the present invention, the method comprises the steps of: (a) anisotropically etching a substrate made of semiconductor to form a trench extending in a direction of the thickness of the substrate; (b) performing a first thermal oxidation to form a first sacrificial oxide film in the trench; (c) removing the first sacrificial oxide film; (d) performing a second thermal oxidation to form a second sacrificial oxide film in the trench after the step (c); (e) removing the second sacrificial oxide film; (f) forming an insulating film comprising a part of a control electrode in the trench after the step (e); and (g) filling the trench to form the control electrode opposed to the substrate through the insulating film comprising the part of the control electrode.
The opening portion and bottom of the trench are rounded by forming the first and second sacrificial oxide films to reduce the defects adjacen

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