Semiconductor device including a reduced stress...

Details Semiconductor device including a reduced stress... Semiconductor device including a reduced stress...

2009-10-08

2011-10-18

Pham, Thanh V (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257SE21295, C257SE23068

Reexamination Certificate

active

08039958

ABSTRACT:
In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.

REFERENCES:
patent: 2003/0025202 (2003-02-01), Mikagi et al.
patent: 2004/0175914 (2004-09-01), Shizuno et al.
patent: 2005/0017376 (2005-01-01), Tsai
patent: 2008/0169562 (2008-07-01), Ke et al.
patent: 102007050610 (2008-05-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2008 054 054.4 dated Jun. 4, 2009.
Translation of Official Communication from European Patent Office re: International Application No. PCT/EP2009/007549 dated Jan. 14, 2011.

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