Semiconductor device including a plurality of memory cells...

Details Semiconductor device including a plurality of memory cells... Semiconductor device including a plurality of memory cells...

2008-11-04

2011-10-11

Pham, Thanh V (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S318000, C257S261000, C257S321000

Reexamination Certificate

active

08035154

ABSTRACT:
A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.

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Notice of Reasons for Refusal mailed on Dec. 15, 2009 issued from the Japanese Patent Office in the corresponding Japanese patent application No. 2008-264848 (and English translation).

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