Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-13
2004-05-11
Fahny, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S900000
Reexamination Certificate
active
06734506
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-314164, filed Oct. 11, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a plurality of kinds of MOS transistors and a method of manufacturing the same.
2. Description of the Related Art
The performance of an LSI is being rapidly improved in accordance with the miniaturization of the device, the improvement in the device performance achieved by the miniaturization, and the improvement in the degree of integration, which are achieved by the development of the process technology. The shortening in the wavelength of the light used in performing a pattern transfer in the lithography process for transferring a pattern onto mainly a semiconductor device greatly contributes to the miniaturization in the size of the device. The shortening in the wavelength of the light is performed by using successively a g-line (436 nm) of an Hg lamp, an i-line (365 nm) of an Hg lamp, a KrF laser (248 nm) and an ArF laser (193 nm). Also, when it comes to a fine design not larger than 0.1 &mgr;m, a light exposure technology using an F
2
laser having a further shorter wavelength and a direct image depicting technology using an X-ray or an electron beam are being studied.
However, the development of the light exposure technology and the image depicting technology using an optical system and an electronic system utilizing light of a shorter wavelength necessitates an improvement in the mechanical accuracy for realizing the miniaturization so as to make it more difficult technically to develop the particular light exposure technology and the image depicting technology.
Under the circumstances, the resolution limit has been improved by improvements in the resist material on to which a pattern is transferred, and by improvements in the illuminating method in the lithography process. Also, it is possible nowadays to form a device of a size not larger than half the wavelength of the light by an ultra high resolution technology called “phase shift method” in which the contrast of the light on a wafer is increased by controlling the phase of the light for each pattern on a reticle.
However, in the phase shift method, the interference of light needs to be skillfully performed to achieve a high contrast, which makes it difficult to form the smallest device size uniformly in respect of various pattern arrangements.
An ultra high resolution light exposure technology, achieved by the “Levenson method”, which is a kind of a phase shift method, will now be described. In the Levenson method, a shifter is arranged such that the phases of the light on both sides of a pair of patterns on a reticle (mask) are reversed to each other so as to improve the contrast. Since the contrast is enhanced in the Levenson method by allowing light beams substantially equal to each other in intensity to interfere with each other, the Levenson method is one of the best methods offered by ultra high resolution technology.
However, if there is a boundary portion in the shifter, the light interferes with the light of the reversed phase even in the region in which a pattern is not formed, with the result that a resist pattern remains, as in the pattern region. In order to avoid this difficulty, in the Levenson method the final pattern formation is generally performed using a reticle called a “trim mask”, in addition to an “alternate mask (Alt mask)” having a shifter formed therein in advance.
FIGS. 1A and 1B
exemplify an Alt mask and a trim mask used for forming the gate electrode of a MOS transistor. In the Alt mask shown in
FIG. 1A
, a light shielding portion
61
consisting of, for example, a Cr film is formed on a quartz plate. A shifter is formed in an open portion
62
in which the Cr film is not formed by removing the quartz plate in that portion by a predetermined thickness. In the trim mask shown in
FIG. 1B
, the light shielding portion
61
alone consisting of a Cr film is formed on the quartz plate.
FIG. 1C
shows an overlay image in which the Alt mask and the trim mask are overlapped with each other.
FIG. 1D
shows a pattern obtained by exposing a resist to light by overlapping the Alt mask and the trim mask, followed by applying a developing treatment. In
FIG. 1D
, a resist pattern
63
is used for patterning the gate electrode. Reference numeral
64
shown in
FIG. 1D
denotes an active region of the MOS transistor.
The specific method of manufacturing a memory mixed LSI in which an inner logic circuit and a DRAM circuit are formed integral by the Levenson method will now be described with reference to
FIGS. 2A
,
2
B to
5
A,
5
B. Incidentally,
FIGS. 2A
to
5
A are cross sectional views each showing a part of the inner logic circuit. Also,
FIGS. 2B
to
5
B are cross sectional views each showing a part of the DRAM circuit. In the DRAM circuit, the STI (shallow trench isolation) structure, the trench capacitor structure, etc. are omitted, and the construction of the gate electrode alone is shown in the drawings.
In the first step, as shown in
FIGS. 2A and 2B
, a p-well region
72
and an n-well (not shown) are formed on a semiconductor substrate
71
in order to form a CMOS transistor. Then, after formation of an isolation insulating film
73
, gate insulating films
74
,
75
are formed on the side of the inner logic circuit and on the side of the DRAM circuit, respectively. Further, a polycrystalline silicon (polysilicon) film
76
is formed on the entire surface, followed by successively forming an antireflection film
77
and a resist film
78
on the polysilicon film
76
.
In the next step, the gate electrode pattern is transferred into the resist
78
by a lithography process by the Levenson method using two masks, i.e., an Alt mask and a trim mask, followed by a developing treatment so as to leave the resist
78
unremoved in the shape as shown in
FIGS. 3A and 3B
.
Then, the antireflection film
77
is selectively removed by an anisotropic dry etching by using the resist
78
as a mask, as shown in
FIGS. 4A and 4B
. Further, a trimming treatment for reducing the sizes of the antireflection film
77
and the resist
78
is performed by isotropic etching, as shown in
FIGS. 5A and 5B
, followed by selectively etching the polysilicon film
76
by using the antireflection film
77
and the resist
78
as a mask so as to form a gate electrode
79
made of a polysilicon film in each of the inner logic circuit and the DRAM circuit. A standard CMOS process is employed in the subsequent step so as to form an LSI.
FIGS. 6A and 6B
show the overlay images formed by the Alt mask and the trim mask used in the method described above.
FIG. 6A
shows the image on the side of the inner logic circuit, with
FIG. 6B
showing the image on the side of the DRAM circuit.
In
FIG. 6A
, a region
81
corresponds to the open portion on the Alt mask, and a region
82
corresponds to an open portion on the trim mask. Also, in
FIG. 6B
, a region
83
corresponds to an open portion on the trim mask. Incidentally, a reference numeral
84
shown in
FIG. 6A
denotes an active region of the MOS transistor.
In the conventional method described above, it is possible to form a fine gate electrode on the side of the DRAM circuit. However, it is necessary to ensure an allowance in the pattern clearance in view of the trimmed portion because a trimming treatment is also applied to the resist pattern on the side of the DRAM circuit.
Also, on the side of the inner logic circuit, it is certainly possible to form a fine gate electrode. However, it is necessary to design the pitch of the gate electrodes in a manner to have an allowance as in the design on the side of the DRAM circuit, with the result that a problem remains unsolved in terms of miniaturization of the device.
It should be noted that, in order to improve the performance of the logic LSI, it
Fahny Wael
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pham Hoai
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