Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-10-24
2004-12-21
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S675000
Reexamination Certificate
active
06833316
ABSTRACT:
This application is based on and claims priority on Japanese Patent application No. 2001-178974, filed on Jun. 13, 2001, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device including a pad of damascene structure and a method of manufacturing the same.
2. Description of the Related Art
The design rule of semiconductor devices becomes finer as the integration density thereof increases. A technical limit is appearing in a method in which after a surface metallic wiring layer of aluminum, wolfram(tungsten), or the like is deposited on a surface of an insulating layer, a resist pattern is formed on the surface metallic wiring layer and then the wiring layer is directly etched.
In place of the method to pattern the surface wiring layer by etching, a damascene process is increasingly used to embed wiring material in wiring grooves and via holes formed by an etching process in a beforehand prepared inter-level insulating layer. The damascene process is suitable to form a narrow wiring layer surrounded by silicon oxide layers.
Aluminum primarily used as wiring material in the prior art is limited with respect to resistance and electro-migration. Thanks to low resistance and a higher limit for the electro-migration, copper is increasingly used. It is difficult to pattern a copper layer by etching. However, copper wiring can be formed by a damascene process.
The known damascene processes include a single damascene process to form a via conductor and a wiring pattern conductor respectively in different processes and a dual damascene process in which a via hole and a wiring groove are first formed and a via conductor and a wiring pattern conductor are formed therein in one process.
A semiconductor integrated circuit device includes pads on its surface for connection thereof to another device. Since wiring is formed by the damascene process, the pad is formed also by the damascene process today.
Referring to
FIGS. 6A
to
6
H, description will be given of a method of forming a single-damascene pad in the prior art. When copper is used as wiring material, for preventing oxidation of an underlie wiring layer in the ashing of a photo resist pattern, it is necessary to use an etching stopper layer of silicon nitride (SiN) or the like having an anti-oxidation function and an etching stopper function. An example of processes of manufacturing a pad section will be described by referring to the drawings.
As shown in
FIG. 6A
, a lower insulating layer d
1
is first formed on a lower wiring w
1
, via holes are formed in the lower insulating layer d
1
, and a lower via conductor v
1
is formed in each via hole.
The lower via conductor v
1
can be formed, for example, by plating a copper layer on a whole surface of an underlie structure and then conducting chemical and mechanical polishing (CMP) process on the plated surface.
As shown in
FIG. 6B
, an etching stopper layer sp is formed with a silicon nitride (SiN) layer of 70-nanometer (nm) thickness on the lower insulating layer d
1
to cover the lower via conductors v
1
. An insulating layer dp of, for example, a silicon oxide film of 2000-nm thickness is formed on the etching stopper layer sp. When it is desired that the insulating layer has a low dielectric constant, silicon oxide including fluorine, porous silicon oxide, or the like is used.
The etching stopper layer sp and the insulating layer dp collectively have a function of an inter-level insulating film. However, the etching stopper sp is a layer for exhibiting functions of preventing oxidation of the via conductors v
1
and of an etching stopper in the etching of the insulating layer dp, and the insulating layer dp primarily serves as an inter-level insulating film.
The dielectric constant of the etching stopper layer sp is higher than that of the insulting layer dp. By increasing thickness of the etching stopper layer sp, the etching stopper function and the oxidation preventive function can be improved. However, this increases capacitance between the wiring layers and hence hinders a high-speed operation of the semiconductor device. Therefore, the thickness of the etching stopper layer sp is desirably reduced to a necessary minimum value.
As shown in
FIG. 6C
, a photo resist pattern PR is formed on the insulating layer dp to define an opening for a pad. The pad opening is defined such that a surface of the lower via conductor v
1
below the pad opening is exposed.
As shown in
FIG. 6D
, the insulating layer dp is etched using the photo resist pattern PR as an etching mask. By using, for example, a parallel plate plasma etching system, the layer dp is etched by dry etching in an atmosphere including C
4
F
8
as a main etching gas. The etching proceeds faster in a peripheral region of the opening than in a central region thereof. As a result of the difference in the etching rate, an etching retardation region RT at a central region (or a sub-trench ST in edge section of the opening) is formed.
The sub-trench indicates a contour formed by the etching rate difference between the wiring edge region and the wiring central region in the etching of a groove for a wiring having a large width. Since the etching rate is higher in the wiring edge region than in the wiring central region, a contour of a groove appears in edge region. The central region becomes higher in level than the edge region.
FIG. 7A
is a graph showing an example of a relationship between the etching rate of the wiring edge region and the wiring central region. The abscissa represents the wiring width in micrometers (&mgr;m) and the ordinate represents the etching rate in nanometers per minute (nm/min). As shown in
FIG. 7A
, while the etching rate is almost fixed in the wiring edge region regardless of the change in the wiring width, the etching rate in the wiring central region has a tendency to become lower as the wiring width increases.
For example, when the wiring width is 30 &mgr;m, the etching rate in the wiring edge region is about 380 nm/min and that in the central region is about 300 nm/min.
In the etching of a silicon oxide layer of about 2000-nm thickness, the etching rate is 380 nm/min in the wiring edge region, and hence 5.26 minutes are required for the just or complete etching of wiring edge region. In contrast therewith, since the etching rate of the wiring central region is 300 nm/min, a silicon oxide layer of 422-nm thickness still remains when the wiring edge region is just or completely etched.
As shown in
FIG. 6E
, when the etching is stopped in a state in which the sub-trench ST appearing in the pad edge section reaches the etch stopper sp, i.e. the insulating layer dp is just etched, the central portion of the insulating layer dp remains as a remaining pattern dpx. Then, the via conductors v
1
below the pattern dpx will not be exposed.
When over-etching is performed to etch the silicon oxide layer completely, the etching stopper layer at the edge region is disadvantageously etched. Assume that deviation of the etching rate in a wafer is about 10%. Then, a period of time necessary to etch the silicon oxide film (2200-nm thickness in the wiring central region) is 6.7 minutes.
The 6.7-minute etching corresponds to the etching of a silicon oxide film of about 2787-nm thickness in the wiring edge region. This results in an over-etching thickness of 787 nm. Assume that a selection ratio between the silicon oxide film and the etching stopper layer is ten. Then, the etching stopper layer is etched up to a depth or thickness of 78.7 nm. If the etching stopper layer has a thickness of 70 nm, the etching stopper layer is completely etched and hence vanishes in the wiring edge region.
As shown in
FIG. 6F
, when the insulating layer dp of the pad central section is completely etched by the over-etching, etching of the sub-trench region ST further proceeds in the pad peripheral section and the etching stopp
Saiki Takashi
Yamanoue Akira
Cao Phat X.
Fujitsu Limited
LandOfFree
Semiconductor device including a pad and a method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a pad and a method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a pad and a method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3319243