Semiconductor device including a nonvolatile memory

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257316, 257317, 257319, 257320, H01L 29788

Patent

active

058250620

ABSTRACT:
Pulse shaped voltage of 5V is applied to a source region 3 at initial phase of erase by a pull back voltage generator 13 connected to the sources region 3. Then, the pulse shaped voltages of 10V and 12V increased under stepwise bases are applied to source region 3 with progress of erasion. Generation of hot-holes at the initial phase of data erasion can be prevented because difference in voltage between the floating gate electrode 5 and source region 3 is decreased. Value of the pulse shaped voltage thus applied is increased for the difference occurred between the floating gate electrode 5 and source region 3 when erasion is in much progress. Thus, it is possible to pull out the stored electrons from the floating gate electrode 5 until the threshold voltages can be set at predetermined values. So that, degradation of characteristics of a gate oxidation layer caused by hot-holes generated with erasion can be prevented.

REFERENCES:
patent: 5200919 (1993-04-01), Kaya
patent: 5402371 (1995-03-01), Ono
patent: 5457652 (1995-10-01), Brahmbhatt
patent: 5477068 (1995-12-01), Ozawa

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