Semiconductor device in which a memory array is refreshed...

Details Semiconductor device in which a memory array is refreshed... Semiconductor device in which a memory array is refreshed...

2009-04-21

2011-10-11

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S236000

Reexamination Certificate

active

08036060

ABSTRACT:
In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM includes a DLL circuit for aligning phase of an internal clock signal with that of an external clock signal that is externally supplied, and a DLL control circuit for exercising control so as to halt operation of the DLL circuit in an interval in which the address signal becomes active one or more times and N−1 times or fewer, this interval being included in an interval in which the signal RAS becomes active N times. The DLL control circuit counts the signal RAS and decodes the value of the count. Operation of the DLL circuit is halted while a prescribed range of count values is being decoded.

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