Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-07-14
2001-05-15
Mis, David (Department: 2817)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S782000, C257S783000
Reexamination Certificate
active
06232661
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a so-called BGA type semiconductor device. More specifically, the present invention pertains to a type of package structure of the semiconductor device preferred in improving the assembly reliability.
BACKGROUND OF THE INVENTION
The BGA (Ball Grid Array) semiconductor device is a type of semiconductor device having a surface assembly type package structure, in which plural ball-shaped solder pieces known as solder bumps are arranged two-dimensionally as the external connecting terminals. Since the connecting terminals can be arranged two-dimensionally, this type of package is preferred for high-density assembly. In particular, BGA has a very important position for the realization of CSP (Chip Size Package) semiconductor devices, that is, semiconductor devices having a package size that is nearly the same size or only slightly larger than the chip size, which have attracted much attention in recent years.
There are various types of BGA, such as the type in which a flexible insulating substrate made of polyimide resin or the like is used as the substrate of the package, and solder bumps are arranged two-dimensionally on one side of the flexible insulating substrate. In this type of semiconductor device, the semiconductor chip is attached to the flexible insulating substrate by an adhesive made of a nonconductive epoxy resin or the like and known as die attaching material. In the manufacturing process, an appropriate number of drops of the die attaching material is applied to the flexible insulating substrate; then, the semiconductor chip is pressed on the substrate, and the die attaching material spreads over the lower surface of the chip. After curing of the die attaching material by heating, necessary wiring is arranged and the semiconductor chip is sealed by a resin. For such a BGA type semiconductor device, assembly is carried out by melting the solder bumps as a whole by reflow after the semiconductor device is mounted on the external substrate (printed board for wiring) by a mounter.
High reliability during the assembly of the semiconductor device is very important. In particular, it has been noted that the assembly reliability is lower than that of the conventional QFP (Quad Flat Package) as explained below. In the temperature cycle test performed for the aforementioned BGA type semiconductor device, cracks may be generated in the joint between the flexible insulating substrate and the solder bumps, in particular, in the joint of the solder bumps right below the outer edge of the chip, and these can lead to the problem of openings in the device. The main cause is due to the difference in the linear expansion coefficient between the semiconductor chip and the external substrate, which generates a shear stress that is concentrated in the aforementioned joint. That is, since the modulus of elasticity of the die attaching material and the flexible insulating substrate between the chip and the external substrate is much lower than that of the chip and the external substrate, the shear stress generated due to the aforementioned difference in the linear expansion coefficient is concentrated in the solder joint. Since the influence of expansion of the semiconductor chip caused by heat is maximum at the edge, the shear stress is maximum in the joint of the solder bumps located right below it. Consequently, the stress in this portion rises, and the assembly reliability of the package is significantly affected.
The purpose of the present invention is to reduce the stress concentration in the joint between the flexible insulating substrate and the solder bumps located right below the outer edge of the semiconductor chip, to avoid the problem of openings (wire breakage) caused by cracks or the like in the joint, and thus to increase the assembly reliability.
Another purpose of the present invention is to improve the assembly reliability of the package without changing the basic shape of the aforementioned package, without a significant change in the manufacturing process and without increasing the manufacturing cost.
SUMMARY OF THE INVENTION
The present invention provides a type of semiconductor device characterized by a semiconductor chip, a flexible insulating substrate which has a first surface and a second surface and which has a conductor pattern on at least one of the surfaces, plural conductor bumps which are arranged two-dimensionally on the first surface of the aforementioned flexible insulating substrate and which electrically connect the aforementioned conductor pattern to an external substrate, and an adhesive layer which is set between the aforementioned flexible insulating substrate and the aforementioned semiconductor chip for attaching the aforementioned semiconductor chip on the second surface of the aforementioned flexible insulating substrate. According to the present invention, the outer edge of the aforementioned adhesive layer extends over the outer edge of the aforementioned semiconductor chip. When the semiconductor device of the present invention is assembled on the external substrate, stress forces, which are caused by a difference in the linear expansion coefficient between the semiconductor chip and the external substrate, and which propagates from the outer edge of the semiconductor chip to the joint of the conductor bumps, is reduced by the adhesive layer extending outward from the aforementioned semiconductor chip, so that shear forces at the joint are reduced.
According to the present invention, in order to reduce the influence of the aforementioned stress forces on all of the conductor bumps located outside the outer edge of the semiconductor chip, it is preferred that the aforementioned adhesive layer extends beyond the area where the aforementioned conductor bumps are located on the aforementioned flexible insulating substrate.
Also, in the present invention, the thickness of the aforementioned adhesive layer is preferably 100 &mgr;m or larger.
Also, in the present invention, it is preferred that the aforementioned adhesive layer has a linear expansion coefficient nearly equal to the linear expansion coefficient of the external substrate on which the aforementioned semiconductor device is assembled.
In this case, for the aforementioned adhesive layer, it is preferred that an adhesive is applied on both sides of an intermediate member which has a linear expansion coefficient nearly equal to the linear expansion coefficient of the external substrate on which the aforementioned semiconductor device is assembled.
Also, in the present invention, it is preferred that the modulus of elasticity of the aforementioned adhesive layer be 10 kg/mm
2
or higher.
Also, the present invention discloses a manufacturing method of a semiconductor device characterized by the fact that it comprises the following steps: a step in which a semiconductor chip is formed; a step that forms a flexible insulating substrate, which has a first surface and a second surface and which has a conductor pattern on one of the surfaces and conductor bumps attached to the first surface; a step in which a film material made of a resin, which is coated on both sides with an adhesive and has a planar size larger than the planar size of the aforementioned semiconductor chip, is bonded to the second surface of the aforementioned flexible insulating substrate; a step in which the aforementioned semiconductor chip is mounted on the aforementioned resin film material so that the aforementioned semiconductor chip bonds to the aforementioned resin film material; a step in which the aforementioned semiconductor chip is electrically connected to the conductor pattern on the aforementioned flexible insulating substrate; a step in which the aforementioned semiconductor chip is sealed; and a step in which the aforementioned conductor bumps are electrically connected to the aforementioned conductor pattern on the first surface of the aforementioned flexible insulating substrate.
REFERENCES:
patent: 5965947 (1999-10-01), Nam et al.
patent: 6040630
Amagai Masazumi
Umehara Norihito
Yajima Kiyoshi
Kempler William B.
Mis David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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