Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2011-03-15
2011-03-15
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S694000, C438S696000, C257SE21169
Reexamination Certificate
active
07906433
ABSTRACT:
A via hole is formed in the interlayer insulating film on a semiconductor substrate, the via hole reaching the bottom of the interlayer insulating film. A filling member fills a lower partial space in the via hole. A wiring trench continuous with the via hole as viewed in plan is formed, the wiring trench reaching partway in a thickness direction. The wiring trench is formed under the condition that an etching rate of the interlayer insulating film is faster than that of the filling member, in such a manner that a height difference between the upper surface of the filling member and the bottom of the wiring trench is half or less than half the maximum size of a plan shape of the via hole. The filling member in the via hole is removed. The inside of the via hole and wiring trench is filled with a conductive member.
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Oryoji Michio
Sakai Hisaya
Fujitsu Patent Center
Fujitsu Semiconductor Limited
Ghyka Alexander G
Nikmanesh Seahvosh J
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