Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-11-12
2004-08-24
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06782522
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
This application relates to and incorporates herein by reference Japanese patent application number 2002-41225, which was filed on Feb. 19, 2002.
FIELD OF THE INVENTION
This invention relates to technology of a terminal and wiring pattern layout when a semiconductor electronic part is mounted on a multilayer circuit board, and technology which enables wide and fine wiring patterns densely to be allocated.
BACKGROUND OF THE INVENTION
There has been a semiconductor device, in which a control circuit IC packaged into a chip size package (CSP) as a control CSP is mounted on a circuit board. Here, the control CSP is connectable by using only a fine wiring pattern for transmitting a signal. Adoption of a multilayer (build-up) circuit board to the control CSP thereby leads to easy wiring design.
However, a CSP for engine control involves a wide wiring pattern for transmitting a power, which needs to find a different wiring design for an efficient layout of the wide wiring pattern.
To deal with the wide wiring pattern, it is proposed as shown in FIG.
7
. Here, a semiconductor electronic part
100
, a CSP, has a fine pitch, so that a corresponding multilayer circuit board
200
has lands
215
between which only one fine wiring pattern
216
b
can pass as seen in the first layer
211
. When the CSP
100
is mounted on the multilayer circuit board
200
, wide wiring patterns
216
a
and the corresponding lands
215
a
are allocated without any specific consideration. Inefficiency of wiring allocation hence causes a broad area for allocating lands in an inner second layer
212
and useless lands
215
c
of no wiring pattern connection. This leads to increase of the layer of the multilayer circuit board and disadvantage in costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device in which an efficient wiring layout is enabled to prevent increase of a layer of a multilayer circuit board. Here, in the semiconductor device, a semiconductor electronic part has a fine pitch and terminals connectable with wide wiring patterns, being mounted on the multilayer circuit board. In the multilayer circuit board, only one fine wiring pattern is passable between lands.
To achieve the above object, a semiconductor device has a semiconductor electronic part in which terminals connectable with wide wiring patterns are allocated in at least the first outermost line among the terminals. Furthermore the semiconductor device has a multilayer circuit board in which lands linked with wide wiring patterns are allocated in at least the first outermost line of at least the first uppermost layer of the multilayer circuit board.
In one embodiment of the invention, a semiconductor device has a semiconductor electronic part in which terminals connectable with wide wiring patterns are allocated in the first and third outermost lines. Furthermore, here, the above terminals allocated in the first and third outermost lines are connectable with lands allocated in the first outermost lines of the first and second uppermost layers of the multilayer circuit board, respectively.
REFERENCES:
patent: 6594811 (2003-07-01), Katz
patent: A-2002-94246 (2002-03-01), None
Iida Taku
Kawamoto Satoru
Yagura Toshiaki
Denso Corporation
Lin Sun James
Posz & Bethards, PLC
Siek Vuthe
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